iMXRT1062 unable to use Quad Timer output as DMA trigger

[zt]

The goal is to use the output of Quad Timer 3, timer 0 as a trigger for DMA channel 0 and channel 1.

Code snippets:

Defines:

<<<

// Quad Timer.

#define QT_ENABLE_TIMER_0_MASK 0x01

// Timer Control Register.

#define QT_COUNT_MODE_MASK 0x2000 // Count rising edge of primary source.
#define QT_PRIMARY_COUNT_SOURCE_MASK 0x1000 // Primary source = IP bus clock/1.
#define QT_SECONDARY_COUNT_SOURCE_MASK 0x0000 // Secondary source ignored.
#define QT_ONCE_MASK 0x0000 // Count repeatedly.
#define QT_LENGTH_MASK 0x0020 // Count until compare, then re-initialise.
#define QT_COUNT_DIRECTION_MASK 0x0000 // Count UP.
#define QT_OUTPUT_MODE_MASK 0x0003 // Toggle output on successful compare.

// Comparator Control Register

#define QT_COMPARE_LOAD_CONTROL_1_MASK 0x0001 // Load upon successful compare with comparator 1.

// DMA uses channels 0 and 1.

#define QT_GPIO_DMA_CHANNEL 0
#define QT_TIMEBASE_DMA_CHANNEL 1

// Crossbar, uses XBAR1 (XBARA).

// Set the select and control registers.
// Map Quad Timer 3.0 (input 32) to XBAR_OUT0 and XBAR_OUT1.
// DMA control: enabled, positive edge.

#define QT_MAP_MASK 0x2020 // Mask for two channels, both input 32.
#define DMA_POS_EDGE_MASK 0x0505 // Mask for two channels, both enabled, positive edge.

// DMA Multiplexer.

// Set using registers DMAMUX_CHCFG0 and DMAMUX_CHCFG1.
//
// ENBL Bit 31 0: Disabled 1: Enabled
// TRIG Bit 30 0: Disabled 1: Triggering enabled
// A_ON Bit 29 0: Disabled 1: Channel always on enabled
// SOURCE Bits 6 .. 0 DMA source (slot number)

#define DMAMUX_CHCFG_A_ON_MASK 0x20000000U
#define DMAMUX_CHCFG_TRIG_MASK 0x40000000U
#define DMAMUX_CHCFG_ENBL_MASK 0x80000000U
#define DMAMUX_SOURCE_30_MASK 0x0000001eU
#define DMAMUX_SOURCE_31_MASK 0x0000001fU

#define ENABLE_DMA_CLK 0x000000c0U // Bits 6,7 CG3 set to 1, enable DMA clock.

>>>

The code to setup the Quad Timer:

<<<

// Reset control registers.

TMR3_CTRL0 = 0x0000; // Control register.
TMR3_SCTRL0 = 0x0000; // Status and control register.

TMR3_ENBL &= QT_ENABLE_TIMER_0_MASK; // Enable timer 0;

// Set load and comparator registers.

TMR3_LOAD0 = 0x0000; // Counting up from zero.
TMR3_CNTR0 = 0x0000;

TMR3_COMP10 = (uint16_t)qt_timebase_dma_config.trigger_rate;
TMR3_CMPLD10 = (uint16_t)qt_timebase_dma_config.trigger_rate;

TMR3_CSCTRL0 |= QT_COMPARE_LOAD_CONTROL_1_MASK; // Load upon successful compare with comparator 1.

// Set main control register.

TMR3_CTRL0 |= QT_PRIMARY_COUNT_SOURCE_MASK; // Clock = IP bus clock/1.
TMR3_CTRL0 |= QT_SECONDARY_COUNT_SOURCE_MASK; // Secondary clock not used.
TMR3_CTRL0 |= QT_ONCE_MASK; // Count repeatedly.
TMR3_CTRL0 |= QT_LENGTH_MASK; // Count until compare, then re-initialise.
TMR3_CTRL0 |= QT_COUNT_DIRECTION_MASK; // Count UP.
TMR3_CTRL0 |= QT_OUTPUT_MODE_MASK; // Toggle output on successful compare.

// Start the timer by setting the count mode.

TMR3_CTRL0 |= QT_COUNT_MODE_MASK; // Count rising edge of primary source.

>>>

and the code to setup the XBARA1 and DMA Mux

<<<

// Signal XBAR Input XBAR Output DMA Source DMA Channel
// ------ ---------- ----------- ---------- -----------
// QT 3.0 -> XBAR1_IN_32 -> XBAR1_OUT_0 -> DMA_REQ_30 -> DMA channel 0
// QT 3.0 -> XBAR1_IN_32 -> XBAR1_OUT_1 -> DMA_REQ_31 -> DMA channel 1

void init_qt_dma_muxs(void)
{
log_entry("At init_qt_dma_muxs()."); // *** Debug ***

// Enable the DMA clock.

CCM_CCGR5 |= ENABLE_DMA_CLK;

CCM_CCGR2 |= CCM_CCGR2_XBAR1(CCM_CCGR_ON); // Turn clock on for XBARA1 ??

// Configure the Crossbar.
// Map QT 3.0 output to XBAR1 outputs 0 and 1.
// This enables the same trigger source to drive two DMA channels.
// DMA channel 0 drives the GPIO.
// DMA channel 1 updates the QT 3.0 period.

XBARA1_SEL0 = 0x0000;
XBARA1_SEL0 |= QT_MAP_MASK; // Connect QT 3.0 to XBAR1 outputs 0 and 1.

XBARA1_CTRL0 = 0x0000;
XBARA1_CTRL0 |= DMA_POS_EDGE_MASK; // Enable DMA, trggered on positive edge.

// Configure the DMA multiplexer.
//
// Note: XBAR1 outputs 0 and 1 map to DMA requests (sources) 30 and 31.
//
// Triggering: Disabled.
// Always ON : Enabled.
// Enabled: Yes
// Sources: 30 and 31

DMAMUX_CHCFG0 |= DMAMUX_CHCFG_A_ON_MASK; // Enable always ON.
DMAMUX_CHCFG0 |= DMAMUX_CHCFG_TRIG_MASK;
DMAMUX_CHCFG0 |= DMAMUX_CHCFG_ENBL_MASK; // Enable mux channel.
DMAMUX_CHCFG0 |= DMAMUX_SOURCE_30_MASK; // Set source to DMA request 30.

DMAMUX_CHCFG1 |= DMAMUX_CHCFG_A_ON_MASK; // Enable always ON.
 DMAMUX_CHCFG1 |= DMAMUX_CHCFG_TRIG_MASK;
DMAMUX_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK; // Enable mux channel.
DMAMUX_CHCFG1 |= DMAMUX_SOURCE_31_MASK; // Set source to DMA request 31.

>>>

I have done a similar function using the PIT and it worked, but swapping the PIT timer for a Quad Timer and changing the XBAR1 routing does not trigger any DMA.

My initial question is: Is it possible for the Quad Timer output to trigger DMA using the XBAR1 link to the DMA multiplexer?

The Quad Timer looks like it is counting as the counter's value changes and re-initialises itself as expected.

Thank you in advance.

[jeremyzhou · Accepted solution]

Hi,
Thank you for your interest in NXP Semiconductor products and for the opportunity to serve you.
I'd like to suggest you test whether the Quad timer can output signal via XBAR firstly, then combine the DMA trigger function later.
Further, I'd highly recommend you use the Quad time to trigger the DMA function instead of through the XBAR module.
Have a great day,
TIC

-------------------------------------------------------------------------------
Note:
- If this post answers your question, please click the "Mark Correct" button. Thank you!

- We are following threads for 7 weeks after the last post, later replies are ignored
Please open a new thread and refer to the closed one, if you have a related question at a later point in time.
-------------------------------------------------------------------------------