iMX95 DRAM timing settings

[simonng]

Hi NXP team,

I want to change the DRAM timing configurations for the iMX95. I think the timing configurations are set by the following codes in the ds file.

freq0 timing 0x5e080100 32 0x020D2100 #TIMING_CFG_3
freq0 timing 0x5e080104 32 0x4866000C #TIMING_CFG_0
freq0 timing 0x5e080108 32 0xF2F08C45 #TIMING_CFG_1
freq0 timing 0x5e08010C 32 0x20488010 #TIMING_CFG_2
freq0 timing 0x5e080124 32 0x0C230308 #DDR_SDRAM_INTERVAL
freq0 timing 0x5e080160 32 0x00000101 #TIMING_CFG_4
freq0 timing 0x5e08016C 32 0x01300000 #TIMING_CFG_7
freq0 timing 0x5e080170 32 0x8B010509 #DDR_ZQ_CNTL
freq0 timing 0x5e080250 32 0x00110A11 #TIMING_CFG_8
freq0 timing 0x5e080254 32 0x00680040 #TIMING_CFG_9
freq0 timing 0x5e080258 32 0x03003E80 #TIMING_CFG_10
freq0 timing 0x5e08025C 32 0x40520200 #TIMING_CFG_11
freq0 timing 0x5e080300 32 0x08110808 #TIMING_CFG_12
freq0 timing 0x5e080304 32 0x00680E02 #TIMING_CFG_13
freq0 timing 0x5e080308 32 0x06040603 #TIMING_CFG_14
freq0 timing 0x5e08030C 32 0x0030001C #TIMING_CFG_15
freq0 timing 0x5e080310 32 0x20610000 #TIMING_CFG_16
freq0 timing 0x5e080314 32 0x0A0A0407 #TIMING_CFG_17

Where can I get the descriptions of the above registers?

Thanks,
Simon

[pengyong_zhang · Accepted solution]

Hi @simonng 

Please refer the  DDRC registers description of i.MX93 RM documentation file. i.mx93 and i.mx95 use the same DDRC IP.

B.R

[pengyong_zhang]

Hi @simonng 

We strongly do not recommend you modify the DDR timing parameters by yourself. Because this may cause unpredictable risks.

What is your purpose about this?

B.R

[simonng]

Hi @pengyong_zhang ,

I need to do some correlation tests on the DRAM devices. So, I want to adjust the timing such as tRCD and tFAW. I want to have the descriptions of the registers. Then I can adjust the value accordingly.

Thanks,

Simon