[iMX93] DSI-HDMI ADV7535 640x480@60Hz support ?

[charleshuang]

Hi NXP Team,

We use adv7535 on our i.MX93 customer board and our device tree is similiar your imx93-11x11-evk.dts. But we can't detect 640x480@60Hz when we execute 'modetest -c'. This issue can also be observed on the imx93 EVK board. Below is the response of modetest tool, please help to solve this problem.

====================================

root@imx93afee420a1:~# modetest -c
trying to open device 'i915'...failed
trying to open device 'amdgpu'...failed
trying to open device 'radeon'...failed
trying to open device 'nouveau'...failed
trying to open device 'vmwgfx'...failed
trying to open device 'omapdrm'...failed
trying to open device 'exynos'...failed
trying to open device 'tilcdc'...failed
trying to open device 'msm'...failed
trying to open device 'sti'...failed
trying to open device 'tegra'...failed
trying to open device 'imx-drm'...done
Connectors:
id encoder status name size (mm) modes encoders
35 34 connected HDMI-A-1 520x320 12 34
modes:
index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
#0 1920x1080 60.00 1920 2008 2052 2200 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
#1 1920x1080 59.94 1920 2008 2052 2200 1080 1084 1089 1125 148352 flags: phsync, pvsync; type: driver
#2 1920x1080 50.00 1920 2448 2492 2640 1080 1084 1089 1125 148500 flags: phsync, pvsync; type: driver
#3 1920x1080 30.00 1920 2008 2052 2200 1080 1084 1089 1125 74250 flags: phsync, pvsync; type: driver
#4 1920x1080 29.97 1920 2008 2052 2200 1080 1084 1089 1125 74176 flags: phsync, pvsync; type: driver
#5 1920x1080 25.00 1920 2448 2492 2640 1080 1084 1089 1125 74250 flags: phsync, pvsync; type: driver
#6 1920x1080 24.00 1920 2558 2602 2750 1080 1084 1089 1125 74250 flags: phsync, pvsync; type: driver
#7 1920x1080 23.98 1920 2558 2602 2750 1080 1084 1089 1125 74176 flags: phsync, pvsync; type: driver
#8 1280x720 60.00 1280 1390 1430 1650 720 725 730 750 74250 flags: phsync, pvsync; type: driver
#9 1280x720 59.94 1280 1390 1430 1650 720 725 730 750 74176 flags: phsync, pvsync; type: driver
#10 1280x720 50.00 1280 1720 1760 1980 720 725 730 750 74250 flags: phsync, pvsync; type: driver
#11 800x600 75.00 800 816 896 1056 600 601 604 625 49500 flags: phsync, pvsync; type: driver
props:
1 EDID:
flags: immutable blob
blobs:

value:
00ffffffffffff004a8b3b2a01010101
1718010380342078ea1ec5ae4f34b126
0e5054a54b008180a940d1c0714f0101
01010101010108e80030f2705a80b058
8a00c48f2100001a000000ff004a3235
374d3936423030464c0a000000fc0044
454c4c2055323431300a2020000000fd
00384c1e5111000a20202020202001c3
020347f35d1f10140513041211161503
020706202101225d5e5f606165665d5e
5f628301000023090707e50f0000e001
6e030c00100018782f00800102030467
d85dc40178c800023a801871382d4058
2c4500132b2100001e023a801871382d
40582c450006442100001e011d801871
1c1620582c250006442100009e00007e
2 DPMS:
flags: enum
enums: On=0 Standby=1 Suspend=2 Off=3
value: 0
5 link-status:
flags: enum
enums: Good=0 Bad=1
value: 0
6 non-desktop:
flags: immutable range
values: 0 1
value: 0
4 TILE:
flags: immutable blob
blobs:

value:

[charleshuang]

Hi @joanxie ,

Any update ?

[charleshuang]

Hi @joanxie ,

Can you provide a detailed explanation of how to add support for the pixel clock? Or does NXP provide a porting guide?
We have attempted to add a set of parameters to the fracn_tbl in clk-fracn-gppll.c, but it did not work.
Upon tracing the code, we discovered that the driver always calculates the closest pixel clock by multiplying the video_pll defined in the device tree by a divider. As mentioned earlier, we are unable to obtain a set of parameters that can support 1080p, 720p, and 480p simultaneously.

--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -78,17 +78,23 @@ struct clk_fracn_gppll {
* The Fvco should be in range 2.5Ghz to 5Ghz
*/
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
- PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
+ PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
+ PLL_FRACN_GP(176225000U, 352, 45, 100, 2, 24),
};

[joanxie]

hi sorry for delay, I took training last week, do you min dump the clock when you set this new pll in the clock driver？and could you share the logfile when you add new pll clock? did you get the error message like "failed to round clock for mode " DRM_MODE_FMT" ??

[charleshuang]

Hi @joanxie ,

I tried making some modifications, VGA works but 1080p broken.
The dmesg and clock_summary can refer the  attatchment.
Thank you !

diff --git a/arch/arm64/boot/dts/freescale/imx93-afee420-a1.dts b/arch/arm64/boot/dts/freescale/imx93-afee420-a1.dts
index 73f54dad8bd6..32ed4281f880 100644
--- a/arch/arm64/boot/dts/freescale/imx93-afee420-a1.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-afee420-a1.dts
@@ -262,7 +262,9 @@ ethphy2: ethernet-phy@1 {

&lcdif {
status = "okay";
- assigned-clock-rates = <445333333>, <148444444>, <400000000>, <133333333>;
+ assigned-clock-rates = <504000000>, <148444444>, <400000000>, <133333333>;
};

diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c
index 439091409438..d8e27bc18005 100644
--- a/drivers/clk/imx/clk-fracn-gppll.c
+++ b/drivers/clk/imx/clk-fracn-gppll.c
@@ -78,17 +78,24 @@ struct clk_fracn_gppll {
* The Fvco should be in range 2.5Ghz to 5Ghz
*/
static const struct imx_fracn_gppll_rate_table fracn_tbl[] = {
PLL_FRACN_GP(1039500000U, 173, 25, 100, 1, 4),
PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6),
PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8),
PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6),
PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
+ PLL_FRACN_GP(504000000U, 168, 0, 1, 0, 8),
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12)
};

[joanxie]

could you tell me how you make 640x480@60 works? and what pixel clock for  1080p do you need ? 1080p@50hz , what different change from 640x480@60 to 1080p@50hz,   just the clock? refer to the dts file, beside of video_pll, I think you should check the second one named IMX93_CLK_MEDIA_DISP_PIX, is it correct for your current display？ I'm not sure what detailed pixel clock you need

[charleshuang]

Hi @joanxie 

About the pixel clock I want to support, it is as mentioned in my previous post.

	pixel_clock_rate	rounded_rate	deviation
1920x1080@60Hz	148500000	148444444	< 0.5%
1280x720@60Hz	74250000	74222222	< 0.5%
640x480@60Hz	25175000	24740741	1.70%

The mode 640x480@60Hz can work probably because the deviation of "25175000 * 20 = 503500000" is less than 0.5% compared to the video_pll (504000000) I set in dts.

I feel that IMX93_CLK_MEDIA_DISP_PIX is not the key because when IMX93_CLK_MEDIA_DISP_PIX is set to 148444444, 640x480@60Hz can be used. Or do you have a clear setting method can share for us (Regarding fracn_tbl, IMX93_CLK_VIDEO_PLL, IMX93_CLK_MEDIA_DISP_PIX, and the relationship between them) ?

[joanxie]

I'm confused with your issue, obviously the pll settings in the dts and the clock dump is for 640x480@60Hz, but now you said 640x480@60Hz   works but 1080p is failed, right? so pls give me 1080p settings and clock dump for 1080p, since 640x480 works now, if I misunderstanding something, pls let me know it, do you fail with 1080p@50? what pixel clock do you need? I have a clock settings for 1080p@60 pixel clock 134.4Mhz

+ PLL_FRACN_GP(537600000U, 112, 0, 1, 0, 5),

&lcdif {
 assigned-clock-rates = <537600000>, <134000000>, <400000000>, <133333333>;

}

[charleshuang]

Hi @joanxie 

Sorry maybe I didn't explain it clearly.
My original question was whether imx93 can support the three modes of resolutions by same video_pll setting ?

[joanxie]

I thought your original question is for how to support 640x480@50 in the current bsp, then new question is for how to support new 1080p mode in the bsp, I misunderstand your question, so your request is for how to add new mode 480p in the current bsp, still need previous mode like 1080p@60 including, right? do you mind give me the new mode after you use command "modetest -c" after you change the new clock for 480p@60? what's the result after you change? you can check the all of supported mode clock should can be divided by the pll clock you set, it's hard to support all of clock they are not can be divided, I also reply to you in another mail

"

[joanxie]

it seems that current bsp doesn't support this as default, firstly you need confirm what pixel clock you need, then check if current pll source for adv7535 supports this or not, if not, you need add by yourself

[charleshuang]

Hi NXP Team,

In imx93-11x11-evk.dts, it's determine lcdif clock-rate as below :

&lcdif {
status = "okay";
assigned-clock-rates = <445333333>, <148444444>, <400000000>, <133333333>;
};

You can see that video_pll is 445333333.

And in dw_mipi_dsi-imx.c, there allow the return value of clk_round_rate() that meets a deviation of +/-0.5%.

dw_mipi_dsi-imx.c:

if ((bridge->ops & DRM_BRIDGE_OP_DETECT) &&
    (bridge->ops & DRM_BRIDGE_OP_EDID)) {
    unsigned long pixel_clock_rate = mode->clock * 1000;
    unsigned long rounded_rate;

    /* Allow +/-0.5% pixel clock rate deviation */
    rounded_rate = clk_round_rate(dsi->pixel_clk, pixel_clock_rate);

    if (rounded_rate < pixel_clock_rate * 995 / 1000 ||
        rounded_rate > pixel_clock_rate * 1005 / 1000) {
        DRM_DEV_DEBUG(dev, "failed to round clock for mode " DRM_MODE_FMT "\n",
        DRM_MODE_ARG(mode));
        return MODE_NOCLOCK;
    }
}

In our case, the resolutions we need to support are :

	pixel_clock_rate	rounded_rate	deviation
1920x1080@60Hz	148500000	148444444	< 0.5%
1280x720@60Hz	74250000	74222222	< 0.5%
640x480@60Hz	25175000	24740741	1.70%

You can see that only the VGA mode doesn't meet the deviation condition. Unfortunately, we cannot find a video_pll value that satisfies all three resolutions. Are there any limitations? Please assist with this as soon as possible, as we have been working on this issue for almost a week! Thank you !

BR,

Sean