iMX8x I/O Sharing

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iMX8x I/O Sharing

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aphillips
Contributor I

Apologies, for the placement of this question, there is no iMX8x section yet.
I am currently doing a H/W design using this processor in a robot application. The M4 core will be dedicated for safety related functions such as E-Stop and Safe Torque Off. There will be a dedicated  'safe side' RTOS for the M4 core.
Given there is only a limited number of dedicated I/O straight to the M4 user core, is it possible to access GPIO and peripherals that connect to the system bus from the M4 user core AND can this I/O be shared between all cores even if they exist on two independent BSP's?

In the documentation for the SOM with regards to the GPIO for the M4 user core, it has the following lines:

RGPIO (Rapid General-Purpose Input/Output) for fast pin I/O capability
      o Dual access (AIPS and AHB access from system peripheral address space)

Not quite sure what 'dual access' or AIPS/AHB means ? Please remember I am a H/W designer not a S/W architect. 
I just want to ensure I distribute the functionality correctly.

Thank you and kindest regards,

Alan Phillips.

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Alan

> is it possible to access GPIO and peripherals that connect to the system bus from

>the M4 user core AND can this I/O be shared between all cores even if they exist

>on two independent BSP's?

yes it is possible. From software point of view it is necessary to use SCFW Porting Kit

Best regards
igor
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