I'm trying to decipher the iMX 8DualX... Reference Manual (Rev E). I'm trying to determine if the IC has the resources I need for my design. Hardware-wise I need the M4 core to have access to 2x UARTs and 1x SPI port. It would be nice if another UART were available for debug. Going by the CM4 interrupt table 12-5, I see that there is only 1 interrupt for a UART. Table 12-6 shows more interrupts I assume for other UARTs. Are some of these UARTs the same as the one in the SCU? Looking at the total low speed communication picture, (please keep in mind that I am currently using only one of the A35 cores, and of course the M core) the M core needs 3x UARTs (including one for debug) and an SPI port. The A35 needs 2 UARTs (including one for debug) and 2x I2C ports. Is that doable?
What is the main function of the SCU? I understand that it has a function in booting up the cores and something to do with power management. In the manual it states that the SCU controls pin muxing (although I don't see anywhere in the manual where pin muxing is described. I see the pin alternate functions described, but not how to select them. My impression is that the SCU doesn't do anything other than control bootup, power management, and pin muxing; and should not be used for anything else - correct?
