iMX8X CSI2RX configuration

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iMX8X CSI2RX configuration

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Senior Contributor I

Our system input video from MIPI-CSI2 interface.

I suppose video data is transferred as MIPI-CSI2 -> Pixel link -> ISI -> DRAM.

In RM, MIPI CSI2 RX block is described as follow figure.

If the above video flow is assumed, do we need any settings for CFG_VID_VSYNC, CFG_VID_HSYNC_FP, CFG_VID_HSYN and CFG_VID_HSYNC_BP registers?

pastedImage_1.png

Because, linux bsp is only set CFG_NUM_LANES, CFG_DISABLE_DATA_LANES and IRQ_MASK registers in MIPI-CSI2 RX block. I would like to confirm that do we need to set other registers of MIPI CSI2 RX block or not.

pastedImage_2.png

We will use a commercial RTOS for product release.  In RTOS case, CFG_VID_VSYNC, CFG_VID_HSYNC_FP, CFG_VID_HSYN and CFG_VID_HSYNC_BP registers are configured. so, I am wondering if I really need these settings.

Target Device is i.MX8DualX.

Best Regards,

Kazuma Sasaki.

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NXP TechSupport
NXP TechSupport

Hi Kazuma,

 See below, please!

For “CFG_VID_VSYNC, CFG_VID_HSYNC_FP, CFG_VID_HSYN and CFG_VID_HSYNC_BP”, the default value 0 is OK.

When receiving MIPI CSI2 line start, line end, frame start, frame end short packages, the CSI2RX needs generate HSYNC and VSYNC signals to internal ISI module, these registers are used to control the HSYNC and VSYNC width. 

Have a nice day!

B.R,

Weidong

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NXP TechSupport
NXP TechSupport

Hi Kazuma,

 See below, please!

For “CFG_VID_VSYNC, CFG_VID_HSYNC_FP, CFG_VID_HSYN and CFG_VID_HSYNC_BP”, the default value 0 is OK.

When receiving MIPI CSI2 line start, line end, frame start, frame end short packages, the CSI2RX needs generate HSYNC and VSYNC signals to internal ISI module, these registers are used to control the HSYNC and VSYNC width. 

Have a nice day!

B.R,

Weidong

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Senior Contributor I

Dear Wigros,

I appreciate your support. I will keep these registers as default value = 0.

Best Regards,

Kazuma Sasaki.

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