[iMX8QM-MEK] SCU uses 4 channel? or 5 channel?

[sushi_happy]

Hi.

The following structure is declared in imx-scu.c (/ kernel_imx / drivers / firmware / imx).

struct imx_sc_ipc {
    / * SCU uses 4 Tx and 4 Rx channels * /
    struct imx_sc_chan chans [SCU_MU_CHAN_NUM];
    struct device * dev;
    struct mutex lock;
    struct completed done;
    bool fast_ipc;

    / * temporarily store the SCU msg * /
    u32 * msg;
    u8 rx_size;
    u8 count;
};

It says "SCU uses 4 Tx and 4 Rx channels", but I think there are 0 to 4 channels.
Isn't it a total of 10 channels (5 Tx and 5 Rx channels)?

"SCU_MU_CHAN_NUM" is "8" by #define.
What should I fix if I want to use all 5 channels?

Please let me know if I am wrong.

[Harvey021 · Accepted solution]

Hi @sushi_happy 

It says "SCU uses 4 Tx and 4 Rx channels", but I think there are 0 to 4 channels. Isn't it a total of 10 channels (5 Tx and 5 Rx channels)?

> The MU has four, 32-bit write-only transmit registers and four, 32-bit read-only receive registers on the Processor B and Processor A-sides. They are not like 0 to 4 channels. Actually with 4 registers for each side.

What should I fix if I want to use all 5 channels?

> 4 Channels by default are designed according to the IP hardware and SoC.

If you want to know more details, I would recommend you to check the 19.9 Messaging Unit (MU) of imx8qm reference manual.

Best regards

Harvey

[sushi_happy]

Thank you, @Harvey021 

I understand that this description refers to the MU of the SCU.

I thought it was a description of LPUART of DMA.