[iMX8QM-MEK] LPUART4 settings

[sushi_happy]

Hi.
How can I use LPUART4(ttyLP4) ?
I made the following changes and the device ttyLP4 is recognized.
However, there is an error in the console message and LPUART4 cannot be used.
Am I missing something or is it wrong?

environment
・Android-11.0.0_2.6.0
・MCIMX8QM-CPU + MCIMX8-8X-BB

changes
・init.rc (/device/nxp/imx8q/mek_8q)
  - Added the following code before "on boot".

    chmod 0777 /dev/ttyLP4

・imx8qm-ss-dma.dtsi (/vendor/nxp-opensource/kernel-imx/arch/arm64/boot/dts/freescale)
  - Added the following code.

    &lpuart4 {
        compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
    };

・imx8qm-mek.dts (/vendor/nxp-opensource/kernel-imx/arch/arm64/boot/dts/freescale)
  - added the following code.

    &lpuart4 {
        pinctrl-0 = <&pinctrl_lpuart4>;
        status = "okay";
    };

    pinctrl_lpuart4: lpuart4grp {
        fsl,pins = <
            IMX8QM_M40_GPIO0_00_DMA_UART4_RX    0x06000020
          IMX8QM_M40_GPIO0_01_DMA_UART4_TX    0x06000020
        >;
    };

boot msg

[ 0.674545] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.677943] 5a060000.serial: ttyLP0 at MMIO 0x5a060010 (irq = 55, base_baud = 5000000) is a FSL_LPUART
[ 1.932236] printk: console [ttyLP0] enabled
[ 1.937290] 5a070000.serial: ttyLP1 at MMIO 0x5a070010 (irq = 56, base_baud = 5000000) is a FSL_LPUART
[ 1.947052] imx8qm-pinctrl scu:pinctrl: pin_config_set op failed for pin 9
[ 1.953939] fsl-lpuart 5a0a0000.serial: Error applying setting, reverse things back
[ 1.961846] 5a0a0000.serial: ttyLP4 at MMIO 0x5a0a0010 (irq = 79, base_baud = 5000000) is a FSL_LPUART

[Yam]

I have the same problem and cannot use LPUART4.

I hope NXP will resolve this issue as soon as possible.

[sushi_happy]

The structure declaration in imx-scu.c (/ kernel_imx / drivers / firmware / imx) says "SCU uses 4 Tx and 4 Rx channels".
I think there are 0 to 4 channels, is that different?
Isn't it a total of 10 channels (5 Tx and 5 Rx channels)?

Is this related to this issue?

[sushi_happy]

"SCU uses 4 Tx and 4 Rx channels"
I learned that this description refers to the MU in the SCU.
The MU has two processors, each with four registers.
There are 8 channels in total.

It is DMA that has 5 LPUARTs.

[sushi_happy]

Please give me a reply...

I am checking the functions called at startup step by step.
After the "... failed for pin9",
In the pinctrl_commit_state function of core.c(/kernel_imx/drivers/pinctrl), the return value "-13" is returned.
Moreover,
According to the description in imx-scu.c(/kernel_imx/drivers/firmware/imx), the meaning of "-13" is "EACCES".
In other words,
It turned out to be a "Permission error (no access)".

What causes this error?
Please tell me how to deal with it.

[Bio_TICFSL · Accepted solution]

Hello Sushi,

The root cause it that pin M40_GPIO0_00 and M40_GPIO0_01 are assigned to M core0 in scfw. When doing pin config, scfw will reject the request from Linux. Please check the variable pad_list in the below section of scfw.

To enable lpuart4 in imx8qm, you might need update the scfw as requirement and disable the uart function in M core0 demo.

regards

[sushi_happy]

Hi, @Bio_TICFSL 

Your advice has solved this problem.

I checked pad_list in boad.c.
And I changed the following section(M core0 in scfw).
  before:     RM_RANGE (SC_P_M40_I2C0_SCL, SC_P_M40_GPIO0_01)
  after:        RM_RANGE (SC_P_M40_I2C0_SCL, SC_P_M40_I2C0_SDA)

I wrote the image built by replacing scfw_tcm.bin.

Now there are no startup errors and ttyLP4 can be used normally.
Thank you, I'm happy.