Hi,
I'm attempting to get de-interlacing using weaving mode working on an iMX8MP. From a previous post, it was suggested to modify the patch on this post (https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/ISL79987-and-adv7180-de-interlace-driver...) to support weaving based de-interleaving. It looks like the patch supports weaving based de-interleaving (the iMX8MP application reference manual seems to suggest that only CHNL_IMG_CTRL[DEINT] needs to be set for either odd/even or even/odd de-interlacing, in addition to the rest of the ISI initialization.
However, when I enable odd/even weaving based de-interlacing (by setting deinterlace_mode = <2> in the device tree), it looks like the ISI IRQ is not firing. This is based on looking at the output of /proc/interrupts and observing that the entry for isi is always 0, and that mxc_isi_irq_handler never gets called.
Additionally, when de-interlacing is disabled (by setting deinterlace_mode = <0>), the interrupt does fire (again, by observing that the isi entry of /proc/interrupts increments, and noticing that mxc_isi_irq_handler does get called).
Do you have any thoughts on what setting could be missing? I have attached the register dump of the ISI of both the weaving based de-interlacing and no de-interlacing.
Thank you for your help.
Mohammed
Hi,
I wanted to see if you had an opportunity to look at my post. Are there any registers that I can look at to see why the ISI interrupt is not being triggered?
Thanks
did you apply all of patches in the community link? but this is for imx8qm, not for imx8mp, and for imx8mp, the capture driver is
Hi,
I did apply the patches that were referenced but whenever I enable weaving based de-interlaced mode, the ISI IRQ never gets triggered. Is there something else that I'm missing (from the documentation, it looks like I only need to set the appropriate DEINT value for the CHNL_IMG_CNTRL register).
I appreciate any help you can provide.
I don't know how you apply these patches, but these aren't for imx8mp, refer to the reference manual, you should set CHNL_IMG_CNTRL, did you dump the register?
Hi @joanxie
The register dump is already shared in the earlier post by @mablabs. Just for your reference here is the dump:
Odd-even:
[ 44.475498] MAB dump_isi_regs -- entry
[ 44.475502] dump_isi_regs -- CHNL_CTRL[0x00]: e0000001
[ 44.475506] dump_isi_regs -- CHNL_IMG_CTRL[0x04]: 20002001
[ 44.475510] dump_isi_regs -- CHNL_OUT_BUF_CTRL[0x08]: 7c707
[ 44.475515] dump_isi_regs -- CHNL_IMG_CFG[0x0c]: f002d0
[ 44.475519] dump_isi_regs -- CHNL_IER[0x10]: 3cfc0000
[ 44.475522] dump_isi_regs -- CHNL_STS[0x14]: 100
[ 44.475527] dump_isi_regs -- CHNL_SCALE_FACTOR[0x18]: 10001000
[ 44.475530] dump_isi_regs -- CHNL_SCALE_OFFSET[0x1c]: 00
[ 44.475534] dump_isi_regs -- CHNL_CROP_ULC[0x20]: 00
[ 44.475538] dump_isi_regs -- CHNL_CROP_LRC[0x24]: 00
[ 44.475541] dump_isi_regs -- CHNL_CSC_COEFF0[0x28]: 00
[ 44.475544] dump_isi_regs -- CHNL_CSC_COEFF1[0x2c]: 00
[ 44.475547] dump_isi_regs -- CHNL_CSC_COEFF2[0x30]: 00
[ 44.475551] dump_isi_regs -- CHNL_CSC_COEFF3[0x34]: 00
[ 44.475554] dump_isi_regs -- CHNL_CSC_COEFF4[0x38]: 00
[ 44.475557] dump_isi_regs -- CHNL_CSC_COEFF5[0x3c]: 00
[ 44.475562] dump_isi_regs -- CHNL_ROI_0_ALPHA[0x40]: 00
[ 44.475569] dump_isi_regs -- CHNL_ROI_0_ULC[0x44]: 00
[ 44.475572] dump_isi_regs -- CHNL_ROI_0_LRC[0x48]: 00
[ 44.475576] dump_isi_regs -- CHNL_ROI_1_ALPHA[0x4c]: 00
[ 44.475579] dump_isi_regs -- CHNL_ROI_1_ULC[0x50]: 00
[ 44.475582] dump_isi_regs -- CHNL_ROI_1_LRC[0x54]: 00
[ 44.475586] dump_isi_regs -- CHNL_ROI_2_ALPHA[0x58]: 00
[ 44.475591] dump_isi_regs -- CHNL_ROI_2_ULC[0x5c]: 00
[ 44.475594] dump_isi_regs -- CHNL_ROI_2_LRC[0x60]: 00
[ 44.475597] dump_isi_regs -- CHNL_ROI_3_ALPHA[0x64]: 00
[ 44.475601] dump_isi_regs -- CHNL_ROI_3_ULC[0x68]: 00
[ 44.475605] dump_isi_regs -- CHNL_ROI_3_LRC[0x6c]: 00
[ 44.475608] dump_isi_regs -- CHNL_OUT_BUF1_ADDR_Y[0x70]: 68700000
[ 44.475613] dump_isi_regs -- CHNL_OUT_BUF1_ADDR_U[0x74]: 00
[ 44.475617] dump_isi_regs -- CHNL_OUT_BUF1_ADDR_V[0x78]: 00
[ 44.475620] dump_isi_regs -- CHNL_OUT_BUF_PITCH[0x7c]: 5a0
[ 44.475625] dump_isi_regs -- CHNL_IN_BUF_ADDR[0x80]: 00
[ 44.475628] dump_isi_regs -- CHNL_IN_BUF_PITCH[0x84]: 00
[ 44.475631] dump_isi_regs -- CHNL_MEM_RD_CTRL[0x88]: 00
[ 44.475635] dump_isi_regs -- CHNL_OUT_BUF2_ADDR_Y[0x8c]: 68400000
[ 44.475638] dump_isi_regs -- CHNL_OUT_BUF2_ADDR_U[0x90]: 00
[ 44.475643] dump_isi_regs -- CHNL_OUT_BUF2_ADDR_V[0x94]: 00
[ 44.475650] dump_isi_regs -- CHNL_SCL_IMG_CFG[0x98]: f002d0
[ 44.475655] dump_isi_regs -- CHNL_FLOW_CTRL[0x9c]: 00
isi interrupt is not generated at all
Thanks
I double confirmed internal team that we don’t support Virtual channel mode and we don’t support interlaced mode;
it seems that the RM isn't correct enough,IMX8QM supports virtual channel but imx8mp doesn't