iMX8MP GPIO Input Detection (via M7 Core)

[JackWiltshire]

Hi,

We wish to detect a 4MHz clock signal on one of the GPIOs by the M7 core to sample in data.

This is being done by reading IO0 of the GPIO4 peripheral.

Here is a snippet of some code we use to profile/test the detection of the clock signal:

What we find is that the M7 fails to accurately detect the signal running at 4MHz.

We can reduce the speed of the signal to toggle at 1MHz in which the M7 GPIO accurately detects the changes just fine, however Increasing the speed, we have problems when reading the GPIO Input signal.

This should not be a problem as we have configured the speed of the M7 to operate at 800MHz with the GPIO peripheral Running at 200MHz:

We are wary that on some ICs there can be GPIO speed settings and wondering if anything like this exists for the M7?

Do you have some metrics for what is the max toggle frequency a GPIO Input signal can accurately trace?

Any help to try and resolve issue would be greatly appreciated.

[mbardi]

In the link below is the kind of App Note I have not been able to find from NXP to describe the read/write latencies for iMX8 Cortex M4/M7  Processors accessing SOC resources.

What is clear is that the read/write latencies are nondeterministic and have a minimum and maximum access time. This will affect hard-real time applications running on M4/M7 Cores to the extent that other solutions and/or vendors may need to be considered instead.

PRU Read Latencies

How To Calculate PRU Read and Write Latencies

[AldoG]

Hello,

To answer your questions

>No, we don't have this for the i.MX8MP Cortex-M7
>For the i.MX8MP Cortex-M7 we do not have such information available.
>More than an issue this seems that it is due to latency when accessing the GPIO register

Best regards,
Aldo.

[mbardi]

Hi Aldo,

>More than an issue this seems that it is due to latency when accessing the GPIO register

Can you tell us how to configure the GPIO register read latency? Where is this documented? Could not find any thing in the TRM Manuals for the Cortex-M7 or iMX8MP. We are seeing it takes 60 Cortex-M7 Clock Cycles to read the GPIO registers which seems way too high.

Is it possible to reduce this number significantly by configuring the M7 Core differently?  For example by modifying the Memory Map. Like mapping the GPIO Registers into the Cortex-M7 Core internal address space using DMA or some other method?

Where can we find a list of the read latencies for accessing Cortex-M7 and iMX8MP peripherals across arbitration buses? Does NXP have any Application Notes on this topic?

Thanks,

Mark

Reference:

https://www.pjrc.com/teensy/DDI0489F_cortex_m7_trm.pdf