iMX8MP + DDR4 Bringup : DRAM PLL dividing parameters

[khang_letruong]

Dear @Zhiming_Liu,

I followed your sharing here : https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/1866MHz-LPDDR4-Porting-Guide/ta-p/145983...

And even the DDR initialization (training) passed successfully on our DDR4 based custom board:

U-Boot SPL 2021.04-lf_v2021.04+g1c0116f3da (Sep 06 2021 - 08:48:23 +0000)
spl_early_init
pca9450_bind: 'pca9450@25' - found regulators subnode
pmic_bind_children for 'pca9450@25' at node offset: 5040
Bound: 0 children for PMIC: 'pca9450@25'
pca9450_bind: pca9450@25 - no child found
pmic_reg_write: reg=c, value=29 priv->trans_len:1, ret=0
pmic_reg_write: reg=10, value=59 priv->trans_len:1, ret=0
pmic_reg_write: reg=1e, value=18 priv->trans_len:1, ret=0
pmic_reg_write: reg=8, value=a1 priv->trans_len:1, ret=0
DDRINFO: start DRAM init
DDRINFO: cfg clk
DDRINFO: DRAM rate 3200MTS
DDRINFO: ddrc config start
DDRINFO: ddrc config done
DDRINFO:ddrphy config start
DRAM PHY training for 3200MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000002]
[PMU Major message = 0x00000001]
[PMU Major message = 0x0000000a]
[PMU Major message = 0x000000fd]
[PMU Major message = 0x000000fe]
[PMU Major message = 0x00000004]
[PMU Major message = 0x00000003]
[PMU Major message = 0x00000009]
[PMU Major message = 0x00000007]
Training PASS
DRAM PHY training for 3200MTS
check ddr_pmu_train_imem code
check ddr_pmu_train_imem code pass
check ddr4_pmu_train_dmem code
check ddr_pmu_train_dmem code pass
[PMU Major message = 0x00000000]
[PMU Major message = 0x00000006]
[PMU Major message = 0x00000005]
[PMU Major message = 0x00000007]
Training PASS
DDRINFO: ddrphy config done
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
>>SPL: board_init_r()
spl_init
SEC0: RNG instantiated
Normal Boot
WDT: Not found!
Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
Can't support legacy image
SPL: failed to boot from all boot devices
### ERROR ### Please RESET the board ###

I am still being stuck with the booting from SD card. Therefore, I would like to double-check if I would need to add support for the clock of the used DDR4's PLL in SPL code as in your tutorial, please ? Please help me about how to identify the PLL dividing parameters such as m, p, s, k as well!

Thanks in advance and best regards,
Khang

[khang_letruong]

[Update]

I think I found how to identify the PLL dividing parameters such as m, p, s, k from the following sharing : https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/iMX-8M-Mini-Register-Programming-Aid-DRA...

However, I use freq setpoints 3200 and 1066 which are already supported by the i.MX u-Boot so I might not need to customize the PLL parameters :

void ddrphy_init_set_dfi_clk(unsigned int drate)
{
        switch (drate) {
        case 4000:
                dram_pll_init(MHZ(1000));
                dram_disable_bypass();
                break;
        case 3200:
                dram_pll_init(MHZ(800));
                dram_disable_bypass();
                break;
        case 3000:
                dram_pll_init(MHZ(750));
                dram_disable_bypass();
                break;
        case 2400:
                dram_pll_init(MHZ(600));
                dram_disable_bypass();
                break;
        case 1600:
                dram_pll_init(MHZ(400));
                dram_disable_bypass();
                break;
        case 1066:
                dram_pll_init(MHZ(266));
                dram_disable_bypass();
                break;
        case 667:
                dram_pll_init(MHZ(167));
                dram_disable_bypass();
                break;
        case 400:
                dram_enable_bypass(MHZ(400));
                break;
        case 100:
                dram_enable_bypass(MHZ(100));
                break;
        default:
                return;
        }
}

Brs,

[Zhiming_Liu]

Hi @khang_letruong 

The PLL Formula and parameters range are descirbed in CCM.You can run the python program to get the correct parameters:

for p in range()
 for ...
  for ...
   for ...
     pll = formula
     if pll= value:
       print p,m,k,s

Does your board can pass under the i.MX DDR Tool?

[khang_letruong]

Dear @Zhiming_Liu ,

Thanks for your reply. 

You can run the python program to get the correct parameters

By the way, what is the python program that you mentioned? Where could I find it?

Does your board can pass under the i.MX DDR Tool?

Our custom board could pass the MSCale DDR Tool v3.30. Did you mean another tool named DDR tool ?

[Zhiming_Liu]

Hi @khang_letruong 

1.You can write the python script refering the formula and parameters range.

2. Our custom board could pass the MSCale DDR Tool v3.30. Did you mean another tool named DDR tool ?

-->It's MSCale DDR Tool v3.30.

3. About log "Can't support legacy image"

You can search this in source code and find it, you should check if you change the image container config or the image on SD is broken.

if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) {
		struct spl_load_info load;

		memset(&load, 0, sizeof(load));
		load.bl_len = pagesize;
		load.read = spl_romapi_read_seekable;
		load.priv = &pagesize;
		return spl_load_simple_fit(spl_image, &load, offset / pagesize, header);
	} else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) {
		struct spl_load_info load;

		memset(&load, 0, sizeof(load));
		load.bl_len = pagesize;
		load.read = spl_romapi_read_seekable;
		load.priv = &pagesize;

		ret = spl_load_imx_container(spl_image, &load, offset / pagesize);
	} else {
		/* TODO */
		puts("Can't support legacy image\n");
		return -1;
	}

[khang_letruong]

HI @Zhiming_Liu ,

Thanks for your confirmation of the python script for calculating the PLL parameters and the MSCale DDR Tool.

3. About log "Can't support legacy image"

You can search this in source code and find it, you should check if you change the image container config or the image on SD is broken.

I even applied the following patch to visualize the header magic word around the code snippet you pointed out :

From 963a020fec06879e09b16c39092dce2e68468892 Mon Sep 17 00:00:00 2001
From: Khang Le Truong <linux4es@gmail.com>
Date: Wed, 18 Jan 2023 08:38:34 +0700
Subject: [PATCH 4/6] ROMAPI: Show header magic

---
 arch/arm/mach-imx/spl_imx_romapi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c
index 6eaecdf600..08f2c452ae 100644
--- a/arch/arm/mach-imx/spl_imx_romapi.c
+++ b/arch/arm/mach-imx/spl_imx_romapi.c
@@ -86,6 +86,7 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
        u32 pagesize, size;
        struct image_header *header;
        u32 image_offset;
+       u32 hdr_magic = 0x00;

        ret = g_rom_api->query_boot_infor(QUERY_IVT_OFF, &offset,
                                          ((uintptr_t)&offset) ^ QUERY_IVT_OFF);
@@ -119,8 +120,13 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image,
                return -1;
        }

+       if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) ) {
+               hdr_magic = image_get_magic(header);
+               printf("ROMAPI: Header magic found 0x%x\n", hdr_magic);
+       }
+
        if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
-           image_get_magic(header) == FDT_MAGIC) {
+           hdr_magic == FDT_MAGIC) {
                struct spl_load_info load;

                memset(&load, 0, sizeof(load));
-- 
2.17.1

And with the booting from the SD card flashed with the firmware including above modification and based on imx8mp-ddr4-evk machine, it showed :

Trying to boot from BOOTROM
image offset 0x8000, pagesize 0x200, ivt offset 0x0
ROMAPI: Header magic found 0xe6666262
Can't support legacy image
SPL: failed to boot from all boot devices

About the image container config you mentioned, I am not sure if mine is correct as I used same as the imx8mp-ddr4-evk (from which I do the adaptation for our custom board) and this later is not available for sale so impossible to confirm if it works because I have a small doubt on the layout of the SD card with the creation of the firmware image for this DDR4 based machine. Another reason of that doubt might be that there's only internal reference design(s) of NXP for the combination of iMX8MP + DDR4 but none from other partners or iMX8MP based SOM makers even-though it should work in theory and based on the documentation. Do you have any suggestion ?

About the SD card potentially broken, I also flashed other one that worked with imx8mp-lpddr4-evk as well.

Best Regards,
Khang