iMX8MM ethernet clock

[raymondman]

Since the product fails the FCC test several times due to the 50MHz produced by the SoC to supply to the PHY LAN8720A, we may need to add the option to use 25MHz crystal for the PHY in the coming layout. But we cannot find any information about which pin of the iMX8MM processor being connected to the reference clock output from the PHY. Also, how should we modify the driver to accept the reference clock? Could anyone give out some advice?

Many thanks in advance!

[riteshmpatel · Accepted solution]

Hi @raymondman,

Hope you are doing well.

Kindly refer to Table 11-96. ENET External Signals in the Reference Manual on Page 3707.

ENET_TD2 can be configured as ENET1_TX_CLK. There are two RMII clock schemes.

1. MAC generates an output 50M reference clock for PHY
2. MAC uses an external 50M clock.

So, the pin which you are using to generate a 50M clock will only be used to accept the 50M clock from the PHY chip.

Thanks & Regards,
Ritesh M Patel