Hi,
I'm currently working on a bringup and stuck on the display. We've connected the MIPI_DSI output to a MIPI_DSI -> eDP bridge (sn65dsi86) while the bridge does not have an external clock connected and thusrequires the clock from the DSI interface. So far I've understood that the DSI clock depends on the pixel clock which in my case is 148.5 MHz (Full-HD Panel, 8 BPP, 60 Hz). This results in a DSI clock of 891 MHz if I've understood everything correctly. My problem now is, that the bridge requires one out of the following five frequencies: 384 MHz, 416 MHz, 460.8 MHz, 468 MHz and 486 MHz.
Is it possible to set an independent clock for the dsi clock lanes?
Thanks,
Christian
Solved! Go to Solution.
Unfortunately that´s not possible to do. Since there is no way to mux the signal.
Thanks for confirmation. So it'll be the external clocks source then.
It seems that other customers had the issues with MlPI-DSI and there is patch for the clocks, let me share the thread that has a functional driver: https://community.nxp.com/t5/i-MX-Processors/Driver-of-ST7703-under-Linux-5-4-3/m-p/1267249/highligh...
Hi Jamesbone,
We've now connected an external clock source to the bridge and now the display works. But it's still theoretically a component that shouldn't be required if the DSI could deliver a specific clock.
My question is, if it is possible to have an independent clock output on the DSI clock lanes (MIPI_DSI_CLK_x) than the one used for the DSI data lanes (MIPI_DSI_DATA_y_x). Going through the block schematics of the clock system, it looks like, this is not possible, but I just wanted to be sure. Do you know that?
Thanks,
Christian
Unfortunately that´s not possible to do. Since there is no way to mux the signal.