iMX8MM - Cortex M4 Debug Console

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iMX8MM - Cortex M4 Debug Console

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c_guerr
Contributor III

 

 

Hi, 


I try to run many exemples provided by the MCUXpresso of Cortex M4 Applications such as:

- RPMSG

- GPT.

Both examples works properly when I run them from U-Boot. For the GPT i see the counter value.
But once the kernel is booted, I have no more messages from the UART I selected for Cortex M4.

For the GPT Problems i thought the original cause would be the same as here: https://community.nxp.com/t5/i-MX-Processors/GPT-capture-sample-on-M4-seems-to-hang-on-Linux-boot/m-...

But I have the same behavior using RPMsg examples.

The ping-pong examples works well in the linux side, getting messages from the Cortex M4. But no UART messages.

Cortex M4 use UART3 and Cortex A53 use UART4.

 

On device tree i've done the following:

 

&ecspi1 {
        status = "disabled";
};

&i2c4 {
        status = "disabled";
};

&pwm3 {
        status = "disabled";
};

&rpmsg{
        /*
         * 64K for one rpmsg instance:
         * --0x40000000~0x4000ffff: pingpong
         */
        vdev-nums = <1>;
        reg = <0x0 0x40000000 0x0 0x10000>;
        memory-region = <&vdevbuffer>;
        status = "okay";
};

&sdma1{
        status = "disabled";
};

&uart3 {
        status = "disabled";
};

 


Disabled ecspi1 as it uses the same pinmuxing of the UART3 and sure, disabling UART3 also.

I've followed the advices of the link show above by reading on registers but i see that UART3 is enabled. In /sys/firmware/devicetree... and so on, uart3 is disabled. So the register have been updated by the CORTEX M4 I guess.

What do you suggest?

Thanks in advance!

 

 

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c_guerr
Contributor III

I found out.

The GPIO5_IO27 was used by the PCIE0 which use the same pad as UART3 RXD.

Sorry for bothering.

在原帖中查看解决方案

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1,192 次查看
c_guerr
Contributor III

I found out.

The GPIO5_IO27 was used by the PCIE0 which use the same pad as UART3 RXD.

Sorry for bothering.

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