iMX8M mini custom board fails to proceed to DDR stress test

[raymondman]

The custom board is built nearly the same as 8MMINILPD4-CPU2-DESIGNFILES except I use Samsung K4F8E304HB 8Gb LPDDR4 SDRAM. I encounter problems when I use mscale_ddr_tool _v3.30. Below are my questions.

1) The output of PMIC PCA9450A does not change after hardware_init. LX1, LX2 & LX3 are the same ~0.85V before and after I download the script. Is it correct?

2) The layout between the iMX8M Mini SoC and LPDDR4 is exactly copied from the reference design. But I can succeed to run the calibration only in 800MHz or below. Can anyone advise what I can do to improve the clock rate?

3) Even though the calibration is done, it fails to proceed to the stress test. The log is as follow,

Downloading file 'bin\lpddr4_train1d_string_v201709.bin' ..Done

Downloading file 'bin\lpddr4_train2d_string_v201709.bin' ..Done

Downloading file 'bin\lpddr4_imem_1d_v201709.bin' ..Done

Downloading file 'bin\lpddr4_dmem_1d_v201709.bin' ..Done

Downloading file 'bin\lpddr4_imem_2d_v201709.bin' ..Done

Downloading file 'bin\lpddr4_dmem_2d_v201709.bin' ..Done

Downloading IVT header...Done
Downloading file 'bin\m845s_ddr_stress_test.bin' ...Done

Download is complete
Waiting for the target board boot...
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:30:14
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled
- Enabling I cache since it was disabled
- Push base address of TTB to TTBR0_EL3
- Config TCR_EL3
- Config MAIR_EL3
- Enable MMU
- Data Cache has been enabled
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x93d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 400MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 15, col size: 10
One chip select is used
Number of DDR controllers used on the SoC: 1
Density per chip select: 1024MB
Density per controller is: 1024MB
Total density detected on the board is: 1024MB
============================================

MX8M-mini: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @400Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @200Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 1D-Training @50Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @400Mhz...
[Process] End of initialization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@400MHz.......Pass
Verifying DDR frequency point1@200MHz.......Pass
Verifying DDR frequency point2@50MHz.......Pass
[Result] OK

============ Step 3: DDR parameters processing... ============
[Result] Done

Success: DDR Calibration completed!!!
DDR Stress Test Iteration 1
--------------------------------
--Running DDR test on region 1--
--------------------------------

t0.1: data i

It suddenly hangs up after running the stress test. The script file has been uploaded. Can anyone have idea what's going wrong?

Many thanks in advance!

[igorpadykov]

Hi Raymond

for that issue one can recheck if "BoardDataBusConfig" in RPA Tool 

MX8M_Mini_LPDDR4_RPA_v19.xlsx

 configured properly.

Best regards
igor

[raymondman]

We use the reference design for our custom board. We also check the original "BoardDataBusConfig" matches the schematic. Could you please confirm if the setting is correct or not? If yes, are there any other suggestions, like adjusting ATxImpedance, ODTImpedance, TxImpedance, etc?

[igorpadykov]

if board suddenly hangs up, this is more probably due to hardware errors:

for example some ddr lines are broken or shorted together. Also this may be caused by power supplies.

Best regards
igor

[raymondman]

Actually the system is reset during the stress test.

The factory has tested the board under X-ray, so it is not open or short problem. We also monitor all voltage rails during the stress test and find everything normal.

We modify the following parameters but the system still resets.

Change MR3 from 0x31 to 0x09. 

ATxImpedance: from 20 to 60. The calibration fails with other values.

ODTImpedance: from 40 to 240

TxImpedance: from 34 to 48. The calibration fails with other values.

Can you tell if the tool configures the PMIC PCA9450 after downloading the script? We do not see any signal on the I2C bus.

[igorpadykov · Accepted solution]

>Can you tell if the tool configures the PMIC PCA9450 after downloading the script?

one can look at "Sample configuration in the front of the .ds script for i.MX 8M Mini PMIC configuration"

on  https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...

Best regards
igor

[raymondman]

Hi igor,

The problem is on our power supply.

Many thanks for your help!

[raymondman]

Hi igor,

I can modify the output voltage of PMIC according to the info you provided. I set BUCK1 and BUCK3 with different combination of 0.8V, 0.85V and 0.9V and find that some combinations may make the system reboot during calibration. For example, the calibration can run successfully with the default PMIC setting at 668MHz, but the system will reboot if I set BUCK1 to 0.8V and BUCK3 to 0.95V.

1.  There is a note shown on the schematic,

BUCK2 default output voltage is 0.85V for A53 1.2GHz. Software will change it to 0.95V for A53 1.6GHz, 1.0V for A53 1.8GHz.
BUCK3 default output voltage is 0.85V for DDRC 1GHz. Software will change it to 0.9V for DDRC 1.2GHz, 0.95V for DDRC 1.5GHz in SPL before DDR initialization.

I also saw on another thread that calibration and stress test can be passed with the default 0.85V for BUCK1, 2 & 3. I am frustrated how the voltage affects the calibration, and even stress test. Do you have more advice?

2. Can I read the registers of the SoC in the DDR script so that I can know the reboot cause?