iMX8M Plus LPDDR4 Config Tool failure

[evancornell]

First design using iMX8M Plus. Lots of prior experience with iMX8M Mini.

I am using NXP i.MX Config Tools v16.1 to check LPDDR4 on new custom hardware.

Using uuu -lsusb, I get the following output when custom board connected to PC:

uuu (Universal Update Utility) for nxp imx chips -- libuuu_1.5.182-0-gda3cd53

Connected Known USB Devices
Path Chip Pro Vid Pid BcdVersion Serial_no
====================================================================
1:3 MX865 SDPS: 0x1FC9 0x0146 0x0002 0D10180085FE787F

So I believe the board is connecting properly via USB.

The problem, I think, is that our custom board is using debug console UART1 on different pins due to muxing limitations.

So I have modified the lpddr4_config.ds to have the following lines:

################step 0: configure debug uart port. Assumes use of UART IO Pads. #####
##### If using non-UART pads (i.e. using other pads to mux out the UART signals), #####
##### then it is up to the user to overwrite the following IO register settings #####
# Custom UART IOMUX config
memory set 0x3033019C 32 0x00000004 #IOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS
memory set 0x303301A0 32 0x00000004 #IOMUXC_SW_MUX_CTL_PAD_SAI2_RXC
memory set 0x303303FC 32 0x00000016 #IOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS
memory set 0x30330400 32 0x00000016 #IOMUXC_SW_PAD_CTL_PAD_SAI2_RXC
memory set 0x303305E8 32 0x00000003 #IOMUXC_SW_MUX_UART1_SEL_RXD

#memory set 0x30330220 32 0x00000000 #IOMUXC_SW_MUX_UART1_RXD
#memory set 0x30330224 32 0x00000000 #IOMUXC_SW_MUX_UART1_TXD
#memory set 0x30330480 32 0x00000016 #IOMUXC_SW_PAD_UART1_RXD
#memory set 0x30330484 32 0x00000016 #IOMUXC_SW_PAD_UART1_TXD
#memory set 0x303305E8 32 0x00000004 #IOMUXC_SW_MUX_UART1_SEL_RXD
sysparam set debug_uart 0 #UART index from 0 ('0' = UART1, '1' = UART2, '2' = UART3, '3' = UART4)

Unfortunately, this is as far as the Logs get when doing the Firmware Init test:

#################### Result for: phy_init ###### Run 1 #############################################Microsoft Windows [Version 10.0.22631.4317]
(c) Microsoft Corporation. All rights reserved.

C:\nxp\i.MX_CFG_v16.1\bin>prompt test-prefix :

test-prefix : "C:/nxp/i.MX_CFG_v16.1/bin/python3/python" "C:/nxp/i.MX_CFG_v16.1/bin/python3/memtool/memtool_entry.py" -t "runtest" -d "C:/ProgramData/NXP/mcu_data_v16/processors/MIMX8ML6xxxKZ/ksdk2_0/mem_validation/ddrc" -p "C:/Users/evanc/AppData/Local/Temp/mem_validation/phy_training_phy_test_0_0_.log" -l INFO "C:/Users/evanc/AppData/Local/Temp/mem_validation/connect.json" "C:/Users/evanc/AppData/Local/Temp/mem_validation/test.json" "C:/Users/evanc/AppData/Local/Temp/mem_validation/phy.json" "C:/Users/evanc/AppData/Local/Temp/mem_validation/ddrc_registers.json" "C:/Users/evanc/AppData/Local/Temp/mem_validation/ddrc_config.json" "C:/Users/evanc/AppData/Local/Temp/mem_validation/ddrc_config_in.json"
INFO memtool.utils.helper *****C:/Users/evanc/AppData/Local/Temp/mem_validation/connect.json
INFO memtool.utils.helper *****C:/Users/evanc/AppData/Local/Temp/mem_validation/test.json
INFO memtool.utils.helper *****C:/Users/evanc/AppData/Local/Temp/mem_validation/phy.json
INFO memtool.utils.helper *****C:/Users/evanc/AppData/Local/Temp/mem_validation/ddrc_registers.json
INFO memtool.utils.helper *****C:/Users/evanc/AppData/Local/Temp/mem_validation/ddrc_config.json
INFO memtool.utils.helper *****C:/Users/evanc/AppData/Local/Temp/mem_validation/ddrc_config_in.json
INFO memtool.phyinit.phy_init Run phyinit for 2020.06\lpddr4
INFO memtool.comm.serial_channel Using serial: COM8
ERROR memtool.comm.serial_channel Cannot receive data from target
ERROR:memtool.comm.serial_channel:Cannot receive data from target (63930ms since start, serial_channel.py:357)
ERROR memtool.common.base_test Application is not waiting for input state.
ERROR:memtool.common.base_test:Application is not waiting for input state. (63931ms since start, base_test.py:548)

Any ideas? If schematic is required, I can provide via email.

Thanks!

[evancornell]

Jorge,

Per @brenolima 's suggestion via email, I tried using the older DRAM tool (https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...).

With that, the process went further, but still failed.

Download is complete
Waiting for the target board boot...

********Found PMIC PCA9450**********
hardware_init exit

*************************************************************************

*************************************************************************

*************************************************************************
MX8 DDR Stress Test V3.30
Built on Nov 24 2021 13:52:12
*************************************************************************

Waiting for board configuration from PC-end...

--Set up the MMU and enable I and D cache--
- This is the Cortex-A53 core
- Check if I cache is enabled 
- Enabling I cache since it was disabled 
- Push base address of TTB to TTBR0_EL3 
- Config TCR_EL3 
- Config MAIR_EL3 
- Enable MMU 
- Data Cache has been enabled 
- Check system memory register, only for debug

- VMCR Check:
- ttbr0_el3: 0x97d000
- tcr_el3: 0x2051c
- mair_el3: 0x774400
- sctlr_el3: 0xc01815
- id_aa64mmfr0_el1: 0x1122

- MMU and cache setup complete

*************************************************************************
ARM clock(CA53) rate: 1800MHz
DDR Clock: 2000MHz

============================================
DDR configuration
DDR type is LPDDR4
Data width: 32, bank num: 8
Row size: 17, col size: 10
One chip select is used 
Number of DDR controllers used on the SoC: 1
Density per chip select: 4096MB 
Density per controller is: 4096MB 
Total density detected on the board is: 4096MB 
============================================

MX8M-plus: Cortex-A53 is found

*************************************************************************

============ Step 1: DDRPHY Training... ============
---DDR 1D-Training @2000Mhz...
[Process] End of CA training
[Process] End of initialization
[Process] End of read enable training
[Process] End of fine write leveling
[Process] End of read DQ deskew training
[Process] End of MPR read delay center optimization
[Process] End of Write Leveling coarse delay
[Process] End of write delay center optimization
[Process] End of read delay center optimization
[Process] End of max read latency training
[Result] PASS
---DDR 2D-Training @2000Mhz...
[Process] End of initialization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D write delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Process] End of 2D read delay/voltage center optimization
[Result] PASS

============ Step 2: DDR memory accessing... ============
Verifying DDR frequency point0@2000MHz......Address of failure: 0x0000000040080000
Data read was: 0x0000000040000038
But pattern was: 0x0000000040000000
Failed
Please modify DDRC/DFI parameters!!!

Using the RPA spreadsheet tool (attached, but doesn't show the modified UART lines), and modifying the UART lines in the ds script, as I had attempted to do thru the Config GUI, ds file is attached.

[JorgeCas]

Hello,

Could you please share your LPDDR connections?

Best regards.

[evancornell]

See attached. Also see updated RPA.. the one I posted previously wasn't saved with the changes I made for our specific LPDDR4.

[JorgeCas]

Hello,

The only thing that I double check is the second chip select that is marked as NC in your LPDDR4 device. Please check that this is not an issue with your IC manufacturer.

Your RPA file is also correctly configured.

From first DDR tool log, I still thinking that the root cause is UART connection since is not able to stablish the connection.

Since it is a custom board design and manufacturing technology are different from NXP reference board, and board related parameters may differ from initial DDR script, so please try tunning:

ODTImpedance

Desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40. Valid values for DDR3L=high-impedance,120,60,40. Valid values for LPDDR4=240,120,80,60,40

TxImpedance

Write Driver Impedance for DQ/DQS in ohm (Valid values for all DDR type= 240, 120, 80, 60, 48, 40, 34)

ATxImpedance

Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all DDR type = 120, 60, 40, 30, 24, 20)

Did you check signal integrity with a lower clock speed?

Best regards.

[evancornell]

Jorge,

I figured this out offline with @brenolima 's assistance. He spotted that my LPDDR part had 2 CS lines and 16 rows instead of 1CS and 17 rows.

I tried with the older tool, and it passed calibration & stress test. DS files attached. I imported the same exact DS file to Config Tools and it failed. So maybe some error / difference between the two tools.

I also tried with attached UART1 ds script on our modified UART1 pins and that worked just fine.

I would, however, like to be kept in the loop if the root cause of this issue is discovered and fixed.

[JorgeCas]

Hello,

The device is correctly detected in serial download mode.

It is not stablishing the UART connection and causing a time out.

After the UART port change in DDR tool you should be able to run the DDR stress test.

Could you please confirm that there is not an issue in UART-USB section of your design?

Best regards.

[evancornell]

Also, there's no issue with USB-UART - using an external FTDI cable.