iMX8M Mini U-boot MIPI D-PHY clock modification

[Kaushal_Verma]

Dear NXP Community,

I am using iMX8M Mini SoC connected to SN65DSI83 MIPI to LVDS converter running on Android 11 OS.

 I have developed a display driver in uboot for the same and could see the proper test pattern on the display when I enable it through SN65DSI83 and could see the fluctuating NXP splash screen which we are getting in EVK boards with inbuilt MIPI to HDMI convertor.

The fluctuation is caused by the MIPI DSI clock frequency Which I am not able to modify by adding it in display-timing. Currently I am getting 1049 MHz in MIPI DSI clock which is not supported by SN65DSI83 convertor and I required 228 MHz in MIPI DSI clock as the same clock is used in Kernel and the display is working fine.

Can anyone please help me to set MIPI DSI clock to 228 MHz in uboot.

Your support is really appreciated.

Regards,

Kaushal Verma

[Kaushal_Verma]

Hi Qmiller,

I am using "MIPI_DSI_PHY_REF_CLK_ROOT" DSI clock and uboot version is 2020.04

Regards,

Kaushal Verma

[Zhiming_Liu]

Hi @Kaushal_Verma 

MIPI_DSI_PHY_REF_CLK_ROOT is a reference clock for DPHY PLL module[you don't need change this clock], you need set correct p, m, s value in DPHY. The sec_mipi_dsim_calc_pmsk function will calculate the p,m,s value for bit clock.

[Kaushal_Verma]

Hi @Zhiming_Liu 

Thanks for the help I did below modification to get clock around 227.8 MHz but the clock is still 1049 MHz.

--- a/drivers/video/nxp/imx/sec_mipi_dsim.c
+++ b/drivers/video/nxp/imx/sec_mipi_dsim.c
@@ -191,7 +191,7 @@
#define PLLCTRL_DPDNSWAP_CLK BIT(25)
#define PLLCTRL_DPDNSWAP_DAT BIT(24)
#define PLLCTRL_PLLEN BIT(23)
-#define PLLCTRL_SET_PMS(x) REG_PUT(x, 19, 1)
+//#define PLLCTRL_SET_PMS(x) REG_PUT(x, 19, 1)

#define PHYTIMING_SET_M_TLPXCTL(x) REG_PUT(x, 15,
#define PHYTIMING_SET_M_THSEXITCTL(x) REG_PUT(x, 7, 0)
@@ -271,6 +271,10 @@
#define MIPI_HBP_PKT_OVERHEAD 6
#define MIPI_HSA_PKT_OVERHEAD 6

+#define PLLCTRL_SET_PMS(x) REG_PUT(x, 18, 0)
+#define PLLCTRL_SET_P(x) REG_PUT(x, 18, 13)
+#define PLLCTRL_SET_M(x) REG_PUT(x, 12, 4)
+#define PLLCTRL_SET_S(x) REG_PUT(x, 2, 1)

/* DSIM PLL configuration from spec:
*
@@ -821,7 +825,7 @@ static int sec_mipi_dsim_bridge_clk_set(struct sec_mipi_dsim *dsim_host)
* Only support '1080p@60Hz' for now,
* add other modes support later
*/
- dsim_host->pms = 0x4210;
+ dsim_host->pms = PLLCTRL_SET_P(5) | PLLCTRL_SET_M(69) | PLLCTRL_SET_S(0);
}

debug("%s: bitclk %llu pixclk %llu\n", __func__, dsim_host->bit_clk, dsim_host->pix_clk);

--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -359,7 +359,7 @@ void enable_display_clk(unsigned char enable)
#ifdef CONFIG_IMX8MN
clock_set_target_val(DISPLAY_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22));
#else
- clock_set_target_val(MIPI_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV22));
+ clock_set_target_val(MIPI_DSI_PHY_REF_CLK_ROOT, CLK_ROOT_ON | CLK_ROOT_SOURCE_SEL(7) |CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV18));
#endif
clock_enable(CCGR_DISPMIX, true);
} else {

Please verify the changes and let me know what else changes need to be done.

Regards,

Kaushal Verma

[Zhiming_Liu]

Can you share the detailed name of DSI clock?