iMX8M Mini SOC is not powered

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

iMX8M Mini SOC is not powered

Jump to solution
466 Views
borisberman
Contributor III

Dear NXP Support Team,

Our client asks the following question:
What happens to the state of the IO pins of the iMX8M Mini SOC when it is not powered?
Will they be in high impedance or something else?

Thank You,
Boris

Labels (1)
0 Kudos
Reply
1 Solution
343 Views
joanxie
NXP TechSupport
NXP TechSupport

got it, according to your description, these IO needs to use buffer to isolate, for what will happen, your client can refer to the data sheet as below

3.2 Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case scenario)

View solution in original post

3 Replies
439 Views
joanxie
NXP TechSupport
NXP TechSupport

refer to the IMX8MM HDG, 

joanxie_0-1712731118689.png

 

0 Kudos
Reply
427 Views
borisberman
Contributor III

Hello NXP TechSupport,

Thank you for your quick response.
I would like to clarify my question.
I didn't mean unused power rail, as described in Table#36 of IMX8MM HDG.
Our client inserts our SOM with iMX8M Mini into his device, and accordingly, SOM is powered from this device. He may have a situation where the SOM is not powered, but part of the GPIO connected to it will be powered. So the question is what will happen to the affected pins If it could cause damage to iMX8M Mini SOC, big leakage current, etc?

Best Regards,
Boris

0 Kudos
Reply
344 Views
joanxie
NXP TechSupport
NXP TechSupport

got it, according to your description, these IO needs to use buffer to isolate, for what will happen, your client can refer to the data sheet as below

3.2 Power supplies requirements and restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to guarantee the reliable operation of the device. Any deviation
from these sequences may result in the following situations:
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst-case scenario)