Dear @joanxie,
Attached is the datasheet of the IMX8, on pages 60 -62 (4.9.4 Toggle mode AC Timing), there is a description regarding the timing and the Toggle DDR Flash.
" For DDR Toggle mode, Figure 21 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI will sample NAND_DATA[7:0] at both the rising and falling edge of a delayed NAND_DQS signal, which is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the device reference manual. Generally, the typical delay value is equal to 0x7 which means a 1/4 clock cycle delay is expected. But if the board delay is big enough".
We understand from the datasheet that the Toggle Flash DDR should be connected instead of the EMMC pin, for example in IMX8 mini :
Could you kindly advise back? a fast response will be highly appreciated.
Many Thanks.
regards,
Shai
