port {
/* MIPI CSI-2 bus endpoint */
imx492_to_mipi_csi2: endpoint {
remote-endpoint = <&imx8mm_mipi_csi_in>;
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
link-frequencies = /bits/ 64 <745000000>;
};
};
The link-frequency is invalid, because the PLL most likely can't produce this number and, what's important, the driver ignores this parameter. I am able to set the aforementioned clocks in a different DT fragment. This is the imx492 part, this is the mipi-csi one:
port@0 {
reg = <0>;
imx8mm_mipi_csi_in: endpoint {
remote-endpoint = <&imx492_to_mipi_csi2>;
data-lanes = <1 2 3 4>;
};
};
Have in mind these two pieces are from the mainline v5.19 kernel, this is why they might look unfamiliar to you. I'm asking about the practical speed limit between the mipi-csi and csi-bridge as that's where the link breaks. Or at least that's what it looks like. In case you can squeeze some more information, this is the relevant clock tree:
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
sys_pll2 1 1 0 1000000000 0 0 50000 Y
sys_pll2_out 5 5 0 1000000000 0 0 50000 Y
sys_pll2_1000m 3 3 0 1000000000 0 0 50000 Y
csi1_phy_ref 1 1 0 1000000000 0 0 50000 Y
csi1_core 1 1 0 500000000 0 0 50000 Y
csi1_root_clk 1 1 0 500000000 0 0 50000 Y
thanks,
Petko