iMX8M Internal pull up with 3.3V NVCC

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iMX8M Internal pull up with 3.3V NVCC

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Senior Contributor II

Hi 

It came to my knowledge from one of our customers that enables a pad internal pull up on GPIO capable pin with 3.3V NVCC the pad is measured as 2.5V.

I have tried it and verified for GPIO3_IO12, GPIO3_IO13 and GPIO4_IO25 - did not test more. For this test, the pad defined as GPIO and internal pull up defined. 

Applying an external pull up of 10K in parallel will measure 3.1V and 4.7K will measure 3.2V - NVCC verified as 3.3V.

Setting the GDIR to output and DR to high measure 3.3V on those pads. 

My question is if you have encountered this issue? 

Is there any other setting I need to perform for the internal pull up so it will pull to 3.3V level? 

I did not find any errata for this issue. 

Will appreciate your prompt response. 

Thanks 

Oded A

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3 Replies

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NXP TechSupport
NXP TechSupport

Hello,

 

  What is exact part number of the i.MX8M device?

Is it custom design?

Was it checked against the Hardware Developer’s Guide and Datasheet(s) recommendations?

 

Have a great day,

Yuri

 

 

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46 Views
Senior Contributor II

Hi 

The part number tested is MIMX8MQ6DVA JZAB 2N14W

This is a custom design reviewed by next in the past - power feed to the SOC is identical to NXP EVK.

The GPIO tested are connected to test point only. No other loading exists.

The design was designed in accordance with i.MX 8MDQLQ Hardware Developer’s Guide, User's Guide. 

Thanks for the quick response

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46 Views
NXP TechSupport
NXP TechSupport

Hello,

 

   The issue in the case takes place because of the following i.MX8M feature:

i.MX8M GPIOs have internal PD(90K), which can’t be disabled.

   PD/PU resistor values on GPIO of i.MX8M 

Regards,

Yuri.

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