I have a 2 lane eDP display panel, which offers Lane0+/-, Lane1+/- and Aux_Ch+/-, there is limited information for this eDP interface and I noticed the iMX8 HDMI interface supports the lane 1, 2 and 4 configuration. But I am uncertain how to connects the data lane and clock signal, is there any information or reference I can follow? Please advise.
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Thank you for your info!
Refer to the document, MX8M_eDP_APP_NOTE.pdf, I can simply follow it and use only the HDMI_TX_P_LN_3, HDMI_TX_N_LN_3, HDMI_TX_P_LN_2 and HDMI_TX_N_LN_2 due to my eDP display panel has two lanes only, right?
I would like to make sure I got this correctly, please kindly confirm.
Many thanks again!!
Did this solution work?
I have tried to find the document "MX8M_eDP_APP_NOTE.pdf" you mentioned but could not, is it possible for you to provide me a link to it please?
The document is called "i.MX8M eDP HW Design APP", sorry for missing the "i" at the beginning.
In addition, I have not implement this in my design yet, but this doc is from NXP and it should be legit.
Unfortunately, I don't think I can share this doc with you here because it stated "NXP CONFIDENTIAL AND PROPRIETARY". So i recommended you to contact NXP to request this doc directly.
You should follow the link in this thread under Igor's reply, you can locate the link and document there. It is still valid.