iMX8 SAI setting both PLL1 and PLL2 frequencies at the same time

[edwardtyrrell]

Hi All,

I would like to know how to set the frequencies of both PLLs in the same SAI node. I have found some patches that allow for run-time parent clock switching depending on whether the audio rate is 8K or 11K based. Using these patches it is possible to render all known audio rates natively which is exactly what we're after.

This snippet of code below shows what we'd like to be able to use:

clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
<&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";

Focusing on the two PLL clocks 'pll8k' and pll11k' these will need to be set to their appropriate frequencies, however at the moment they default to the audio_pll1 and audio_pll2 frequencies of 393216000 and 361267200 respectively. 

Since this configuration is a little non-standard we cannot use assigned-clock-parents and assigned-clock-rates properties to set the PLL frequencies (have tried but they don't work). Is there a simple way to set both frequencies within this particular SAI node? We've tried a number of things within the node declaration and also outside the node such as in imx8mm.dtst clk: clock-controller node etc. Nothing seems to work so far..

Thanks. 

[joanxie]

do you mean you need assign two PLL to the assigned-clock-parents? if yes, I don't think can support this, for more detailed information, pls refer to the reference manual and clock source code as below

"https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/clk/imx/clk-imx8mm.c?h=lf-5.15.y"

[edwardtyrrell]

Hi @joanxie 

These are the links regarding the patches for using both PLLs and the iMX8 to get all possible native audio rates. As you can see they aree fairly recent.

https://lore.kernel.org/lkml/1656567554-32122-2-git-send-email-shengjiu.wang@nxp.com/ 

https://lore.kernel.org/lkml/1656567554-32122-5-git-send-email-shengjiu.wang@nxp.com/ 

The comments explain the ability to change them at run time. The patch writer is actually from nxp!

I'm starting to think is there a need to decrease the PLL frequencies ad the ratios are worked out in fsl_sai.c anyway... 

Thanks.

[edwardtyrrell]

Hi @joanxie 

Yes, both in the same SAI device tree declaration. 

Regards the clk-imx8mm.c you sent, what does this bit of code actually do? Does is actually start the specific clock or just set up the gating and muxing?

What do hws[] and  mx_clk_hw_pll14xx() do internally. If I can understand those I might be able to trace the clock setting a little better.

For example:

hws[IMX8MM_AUDIO_PLL2] = imx_clk_hw_pll14xx("audio_pll2", "audio_pll2_ref_sel", base + 0x14, &imx_1443x_pll);

Thanks.

[joanxie]

pls refer to this

"https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/clk/imx/clk-pll14xx.c?h=lf-5.15.y"