iMX8 SA1 MCLK as input puzzle

[edwardtyrrell]

Hi,

I'm having some difficulty getting SAI1 MCLK to act as an external clock input in order to drive the SAI1 I2S signals to our codec. I've tried a number of things based on other users experiences on this forum and have researched the iMX8 Mini Applications Processor Reference Manual extensively. When it comes to the manual and sections describing the CCM, SAIs, clock muxing there appears to be a bit of inconsistency on how these sections tie together.

So to start off, the manual states my objective is possible:

13.1.1.4.1 SAI Master Clock Inputs/Outputs
"When configured as an input, the external input to the pad will be used as SAIn_MCLK and is routed to SAIn_MCLK_IN, which can be used as master clock for SAI."

The above excerpt states that the MCLK pin can be used as the SAI 'master clock'; I assuming this will be clock source for all I2S signals (SCLK,LRCK,DATA) etc, relative to frequency for MCLK input? (Y/N?)

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Page 3895 Figure 13-1 clearly shows how MCLK can be sourced from an external clock source resulting in SAIn_MCLK signal (alias SAIn_MCLK_IN)

The general view on this forum is that there are two mux's that require setting to route an externally applied clock to SAI1.

IOMUXC_GPR_GPR2 -> GPR_SAI1_EXT_MCLK_EN which sets the direction control of the corresponding pad as and input
IOMUXC_GPR_GPR6 -> GPR_SAI1_SEL1 (bit 5) IPG_CLK_SAI_MCLK of SAIn source select being SAIn.MCLK

https://community.nxp.com/t5/i-MX-Processors/iMX8M-Mini-How-to-use-MCLK-pad-as-master-clock-input/td... 

Apparently setting these two registers should result in the externally applied clock (on MCLK pin) being routed SAI1 for use as the master clock. According to the advice on this forum
these registers should be set in u-boot or at least sometime before the SAI and 12C drivers get probed to prevent lockups etc.

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Throughout the manual the clock names appear to alter somewhat depending on chapter and topic which makes it difficult to trace certain clocks around the manual.

For example:
Page 3895 - Each SAI module supports up to 3 master clock inputs - SAIn_MCLK[1] to SAIn_MCLK[3]
Page 3896 - Figure 13-2 which follows uses - ipg_clk_sai_mclk[1] to ipg_clk_sai_mclk[3].

Are these the same?

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To use SAI1 MCLK pin as an input, providing these two IOMUX_GPR registers are set, what else needs to be added, i.e in the device tree?
I have seen a few forum users NOT use "assigned-clock-parents" and by what I've worked out that's correct as this property sets the 'clock source' in the CCM mux as per the diagram on page 313 of the manual. Using an external MCLK there is no need for CCM clocks such as 24M_REF_CLK, AUDIO_PLL_CLK etc. Setting the two IOMUX_GPR registers above would switch out that mux entirely.

That leaves the question of what to put in the device tree. Some users use only one set of clock definitions like below. Exactly what are IMX8MM_CLK_SAI1_IPG and IMX8MM_CLK_SAI1_ROOT is unclear in relation to the manual.
Another clock with little description is IMX8MM_CLK_SAI1_SRC. Lots of clock definitions with little information describing them.

Using more that one clock to drive the SAI (as per page 3895) appears to correlate to mclk1,2,3 below but as afar as I have researched there no mention of the "bus" SAI clock in the manual. How does a 'bus' clock do in respecting a SAI?

clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
        <&clk IMX8MM_CLK_SAI1_ROOT>,
        <&clk IMX8MM_CLK_DUMMY>,
       <&clk IMX8MM_CLK_DUMMY>;
clock-names = "bus", "mclk1", "mclk2", "mclk3";

I'm NOT using 3 clks as this example, only one. I2S transmit - no receive.  A straight forward audio codec that only produces audio. 

Considering the two IOMUX_GPR registers described above what MX8MM_CLK_xxxx define would be appropriate to use to represent the clock coming from the external MCLK pin? 

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So my actual objective is simple, I'd like to use the MCLK on SAI1 as an input from an external clock source to clock the internals of the SAI thus providing synchronised SCLK and other I2S signals. What am I missing? The furthest I can get is a build that stalls at the probing of the SAI; I'm assuming it's missing a vital clock (tested with the two IOMUX_GPR registers set and external clock applied to the MCLK pin).

As a side point, there has been mention of a clock patch that tidies up the clocking but this could be a red herring.

My build is Yocto Honister - kernel 5.15.5
Manual - i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020