iMX8 - LPDDR4 RPA tool + DDR Tool

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iMX8 - LPDDR4 RPA tool + DDR Tool

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NathanSmith
Contributor I

I have a question regarding the ODTImpedance (line 613 of Register Configuration, RPA tool V28).  This appears to be an input to the calibration / training algorithms in the DDR tool and not a direct register configuration. 

Is this parameter for the desired termination of the command bus (CA, CS) or the desired termination of the data bus (DQ, DM)?

What effect does this parameter have on the calibration process and training process? 

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NathanSmith
Contributor I

Thanks.  We have been through the DDR tool documentation (Rev V2.0.0) and the developers guide (Rev 1) and it seems ambiguous to which bus this parameter is referring too.  I could not find any reference to this parameter on the Summary page you referenced (this is where we downloaded all the tools from).  It does not give guidance for this parameter.  The impedance controls are bus independent on the LPDDR4 device so I would expect this is referring to the data bus or the command bus but not both at the same time.  It does not make mention to how or what this parameter is controlling in the calibration process.  We were expecting a clearer definition or better guidance for the parameter for such an important part of the design and verification process.  The other parameters are more clearly defined.

Through experimentation I have observed the current on the 1.1V DRAM supply change with this parameter.  Is the method to simply guess / tune the value to the lower power consumption while still passing the stress tests across the operating temperature range?

 

 

 

 

 

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Yuri
NXP TechSupport
NXP TechSupport

@NathanSmith 
Hello,

  I meant the following:

4.4 Run DDR Calibration and generate DDR initial code

Please follow chapter 3 to run DDR calibration and stress test
with your board specific script. If there is no problem, Congratulations,
you can generate DDR initial code now. In initial DDR script, RPA tool
always use NXP reference board related parameters. Your board design and
manufacturing technology are different from NXP reference board, and board
related parameters may differ from initial DDR script. If DDR calibration failed,
you can try to modify following DDR parameters in script.

TrainInfo This parameter controls DDR training debug message. The default value is 0xc8,
which means only display stage completion message. You can change to 0x05 to get detailed
debug message when DDR training failed.

ODTImpedance Desired ODT impedance in Ohm. Valid values for DDR4=240,120,80,60,40.
Valid values for DDR3L=high-impedance,120,60,40. Valid values for LPDDR4=240,120,80,60,40

TxImpedance Write Driver Impedance for DQ/DQS in ohm (Valid values for all DDR type= 240, 120,
80, 60, 48, 40, 34)

ATxImpedance Write Driver Impedance for Address/Command (AC) bus in ohm (Valid values for all
DDR type = 120, 60, 40, 30, 24, 20)

PhyVref This parameter is used for 1D training process. You can refer to DDR datasheet for
detailed meaning.

Mode Registers (MR0~MR22) There are different meanings for different DDR types. Please refer
to DDR datasheet for detailed information. Remember don’t manually modify the Mode Registers.
Instead, please modify Mode Registers in RPA tool. Because there may be other parameters related
to the Mode Registers.

Note - no more parameters, available for customers.

Regards,
Yuri.

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Yuri
NXP TechSupport
NXP TechSupport

@NathanSmith 
Hello,

  Please use section 4.4 (Run DDR Calibration and generate DDR initial code)
of “MSCALE_DDR_Tool_User_Guide.pdf”.

 

https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...

 

Summary Page:

 https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Family-DDR-Tool-Release/ta-p/110...

 

Regards,
Yuri.

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