iMX8 Display Port error on get training status

[zemagi]

I want to get DP working on iMX8QM board.

Linux  version 5.4.142 (Dunfell).

resolution 1920x1080@60 

The system fails on get the training status. 

Spoiler

[ 1.250766] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 1.257412] [drm] No driver support for vblank timestamp query.
[ 1.263458] imx-drm display-subsystem: bound imx-drm-dpu-bliteng.2 (ops dpu_bliteng_ops)
[ 1.271648] imx-drm display-subsystem: bound imx-drm-dpu-bliteng.5 (ops dpu_bliteng_ops)
[ 1.280309] imx-drm display-subsystem: bound imx-dpu-crtc.0 (ops dpu_crtc_ops)
[ 1.288021] imx-drm display-subsystem: bound imx-dpu-crtc.1 (ops dpu_crtc_ops)
[ 1.295730] imx-drm display-subsystem: bound imx-dpu-crtc.3 (ops dpu_crtc_ops)
[ 1.303484] imx-drm display-subsystem: bound imx-dpu-crtc.4 (ops dpu_crtc_ops)
[ 1.319571] [drm] Started firmware!
[ 1.339861] [drm] HDP FW Version - ver 34559 verlib 20560
[ 1.411752] imx-drm display-subsystem: bound 56268000.hdmi (ops cdns_mhdp_imx_ops)
[ 1.420000] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 0
[ 1.456014] [drm] Mode: 1920x1080p148500
[ 1.519614] [drm] DP link id: , 0x0 0x0 0x0 0x0 0x0 0x0
[ 1.521780] [drm] DP revision: 0x12
[ 1.521785] [drm] DP rate: 270000 Mbps
[ 1.521788] [drm] DP number of lanes: 4
[ 1.521792] [drm] DP capabilities: 0x1
[ 1.826429] cdns-mhdp-imx 56268000.hdmi: [drm:cdns_mhdp_train_link] *ERROR* get training status failed: -22
[ 1.826442] cdns-mhdp-imx 56268000.hdmi: [drm:cdns_mhdp_train_link] *ERROR* Failed to get training stat -22
[ 1.826457] cdns-mhdp-imx 56268000.hdmi: [drm:cdn_dp_bridge_enable] *ERROR* Failed link train -22
[ 2.012549] imx-drm display-subsystem: fb0: imx-drmdrmfb frame buffer device

DTS is the following:

Spoiler

&hdmi {
compatible = "cdn,imx8qm-dp";
firmware-name = "dpfw.bin";
lane-mapping = <0x1b>;
status = "okay";
};

&irqsteer_hdmi {
status = "okay";
};

&ldb1_phy {
status = "disabled";
};

&ldb1 {
status = "disabled";
};

&hdmi_lpcg_i2s {
status = "okay";
};

&hdmi_lpcg_gpio_ipg {
status = "okay";
};

&hdmi_lpcg_msi_hclk {
status = "okay";
};

&hdmi_lpcg_pxl {
status = "okay";
};

&hdmi_lpcg_phy {
status = "okay";
};

&hdmi_lpcg_apb_mux_csr {
status = "okay";
};

&hdmi_lpcg_apb_mux_ctrl {
status = "okay";
};

&hdmi_lpcg_apb {
status = "okay";
};

&hdmi_lpcg_i2c0 {
status = "okay";
};

&hdmi_lpcg_lis_ipg {
status = "okay";
};

&hdmi_lpcg_pwm_ipg {
status = "okay";
};

Any suggestion?


thanks

[joanxie]

I couldn't open your dts and training status, do you mind uploading again?

[zemagi]

here are the files.

[joanxie]

did your board design based on imx8qm lpddr4 validation board? lane mapping is based on your HW design, do you mind sharing your dp port connection schematic? this is imx8qm dp board dts file

"https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8qm-lpddr4-val-d..."