iMX7D : Which pin do I use for inputting external clock signal ?

[koichisakagami]

Dear community,
We have been developing our product with iMX7D.
I have a question about  iMX7D PIN name for inputting external clock signal .

In Reference Manual IMX7DRM Rev. 0 , 5.3.2 Functional Description,
it is described that
Crystal oscillator provides selection control switches to either select crystal clock or
external clock through PADI pin.

[Question]
    Which is the PADI pin ?
    Is it XTALI pin ?
    Or are they CCM_CLK1_P/CCM_CLK1_N , CCM_CLK2 pin ?

Best Regards,
Koichi Sakagami

[Yuri]

Hello,

  From the i.MX7 hardware design guide : "External kilohertz source If feeding an

external clock into the device, RTC_XTALI can be driven DC-coupled with RTC_XTALO

floated or driven with a complimentary signal.

   The voltage level of this driving clock should not exceed the voltage of VDD_SNVS_CAP
and the frequency should be <100 kHz under typical conditions. Do not exceed VDD_SNVS_CAP
or damage/malfunction may occur. The RTC_XTALI signal should not be driven if the VDD_SNVS_CAP
supply is off. This can lead to damage or malfunction.

   For RTC_XTALI VIL and VIH voltage levels, see the latest i.MX 7 series datasheet available
at nxp.com. Note that if this external clock is stopped, the internal ring oscillator starts automatically."

http://www.nxp.com/files/32bit/doc/user_guide/IMX7DSHDG.pdf

Have a great day,
Yuri

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[koichisakagami]

Dear Yuri,

Thank you for your reply.

I  check the IMX7DSHDG .

In User's Guide IMX7DSHDG Rev. 0 , 4.3. Checking for clock pitfalls,

it is described that

CLK1_P/N/CLK2 can be used as oscillator inputs for low jitter special frequency sources.

[Question]

Is it possible to use the CLK1_P/N/CLK2 as PLL reference clock ?

Best Regards,

Koichi Sakagami

[Yuri · Accepted solution]

Hello,

From i.MX7 RM :

   "Both CLK1P/N and CLK2 can take input clocks from outside of the SoC and provide

them to the PLLs or to the other modules, or they can take the outputs of the PLLs and

provide them outside of the SoC as a functional or reference clock."

  "Reference input clock for any of the PLLs could be selected individually by the

BYPASS_CLK_SRC feed of the PLL control register. Each PLL can use one of the

following clock source as its reference clock:

• 24MHz clock from XTAL.

• External reference clock from CLK1P/N.

• External reference clock from CLK2."

Regards,

Yuri.