iMX7D Sabre power-down scheme

[erlendhestnes]

Hi,

We have a CPU-board design based on the iMX7D Sabre evaluation board (MCIMX7D-SABRE). In recent light of some strange power-on / power-off behaviour with our board we have some questions about the purpose of U37 (TPS3808G30DBVT) in the Sabre Evaluation board. It would be very helpful for our debug effort if you could shed some light on how this specific part of the system is intended to work.

• Why does U37 both sense and is being supplied by the PMIC VSNVS output? How is this safe?
• Why is U37 set to have a threshold voltage of exactly 2.79V?
• Is U37 just a way of providing safe and reliable ORing of the watchdog signals (MX7_RST_B, GWDOG_RST_B etc.)? 

During a power-down (with sufficient capacitance attached on the PSU_5V0 rail) we have seen the following:

1. Power is removed and the voltage starts to drop slowly.
2. When the voltage reaches 2.79V the PWRON signal from U37 is pulled low (as it should). 
3. The PMIC then transitions into its OFF state, thus consuming very little current.
4. The low current consumption of the PMIC causes the input voltage to rise above 2.79V again due to the reduced load of the system.
5. After approx 189ms (which is the the timeout set by C383), U37 asserts the PWRON signal again (as it should)
6. This cycle continues for a while, causing the PWRON signal to look like a pulse-train.  

Best regards,

Erlend

[Yuri]

Hello,

   As I understand the following circuit is considered.

 The mentioned circuit serves to meet general recommendation to remove power (voltage source)

for all components on  the board in case of a processor reset. This avoids having to determine if a
component critical to rebooting the processor is in the necessary state to support a reboot.

So, total system POR may be recommended for reboot (via WDOG).

  As for Your case, please check if VSNVS voltage is (always) provided. 

Have a great day,
Yuri

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