iMX7D : How to determine eLCDIF timing ?

[koichisakagami]

Dear community,
We have been developing our product with iMX7D.

I am planning to use LCDIF MPU mode.

I check an eLCDIF timing with Figure 13-13 "Timing in write mode of 6800 and 8080 protocols"
in the Reference Manual IMX7DRM (page 3639).

I know that LCD Interface Timing Register (LCDIFx_TIMING) is used for setting to CMD setup/hold and DATA setup/hold. But I can not find a register constituting the timing except LCDIFx_TIMING register.

[Question]
    So,
    Could you tell me how to determine the timing  as follows.
        1. timing width (W1 + W3)
        2. timing width (W2)
        3. timing point where LCD_CS signal is negated .
        4. timing width from negated LCD_CS signal to asserted LCD_CS signal .

Best Regards,
       Koichi Sakagami

[art · Accepted solution]

1-2. W1, W2 and W3 are the internal delays, caused by data transfer delay on the processor's internal bus. These delays are variable by their nature, but relatively small versus the period of the DISPLAY_CLK clock that defines the LCDIF timings in the MPU mode.

3. On the Figure 13-13, there are the TDSW and TDHW parameters, that are the Data Setup and Data Hold times, as defined in the LCDIF_TIMING register, correspondingly. As it can be seen, these parameters, together with small W1, W2 and W3 delays, define the pulse length of the LCD_CS signal.

4. As shown on the Figure 13-13, the LCD_CS signal's assertion point is defined by the TCS and TCH parameters, that are the Command Setup and Command Hold times, as defined in the LCDIF_TIMING register, correspondingly.

Have a great day,
Artur

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