iMX7 CM4 LMEM DDR Caching

[dogisfat]

Yuri,

I understand that it is highly recommended to use 0x00000000 - 0x1FFFFFFF for code. Unfortunately to have reasonable performance using DDR memory all data (code and data) must come from the system bus as has been experimentally found here:

https://blog.printk.io/2017/05/i-mx-7-cortex-m4-memory-locations-and-performance/

My application requires reasonable execution performance (no more than ~2x slower than executing from TCM) and reasonable code space (more than TCM+OCRAM). Therefore I have to use the system bus and run code out of DDR.

When I configured the MPU to have 0x8000_0000 - 0x801f_ffff as catchable and all following memory (0x8020_0000 -> )as uncatchable AND disable instruction access (bit 28 of MPU_RASR register) the M4 core faults with a IACCVIOL. So clearly the cache controller is messing with memory outside of the documented cacheable region. This is unexpected behavior.

What I am looking for with this request is documentation that I can follow and not experience unexpected behavior. What can I do to help facilitate that?

Thanks,

Allen

[Yuri]

Hello,

  We have checked at on IMX7D(Rev 1.3) and doesn't find issue with the address 0x8020_0000

for code section with cache enabled/disabled.

  Meanwhile, we do have the suggestion as per the below,

One can change the m_data to "0x9ff00000" in the platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ocram.ld,

then follow the steps to load binary into the OCRAM from Getting started doc of FreeRTOS bundle.

If code size(text) is too higher that it cannot fit into the OCRAM then one can change DDR linker script from file platform/devices/MCIMX7D/linker/gcc/MCIMX7D_M4_ddr.ld as per below,

m_interrupts ORIGIN = 0x9ff00000, LENGTH = 0x9ff00000

m_text ORIGIN = 0x9ff00240, LENGTH = <As per need>

m_data ORIGIN = 0x9ff08000, LENGTH = <As per need>

Then just follow the steps to load the binary at address "0x9ff00000" into external RAM.

Hope the above information will be helpful.

Have a great day,

Yuri

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