Hi everybody,
I'd like to configure the pins of the iMX6sx processor in order to assign some peripheral to the M4 Core and other to the A9 Core.
I'm trying to use the desktop version of "Config Tool for i.MX" v.8.0. I started creating a new configuration, choosing this:
Processor: MCIMX6XxxVM
Part number: MCIMX4EVM10AB
Core: Cortex-A9
SDK Version: i_MX_1_0
I created a functional Group "BOARD_A9_InitPins" and routed the UART1 interface.
Then i tried to add "BOARD_M4_InitPins" functional group for the M4 Core, in this way (notice the section Core: Cortex-M4):
After selected this new functional group and routed the UART2 peripheral I see this situation:
- 5 files are generated: imx6sx-board.dtsi, pin_mux.c (@Cortex-A9), pin_mux.h (@Cortex-A9), pin_mux.c (@Cortex-M4), pin_mux.h (@Cortex-M4)
- the following warning message is provided:
Issue: Function core Cortex-M4 differs from the selected active core Cortex-A9.
Level: Warning
Type: Tool problem
Tool: Pins
Origin: Pins:BOARD_M4_InitPins
Resource: Core Booting Role
Information: -
Does it mean that it is not possible to route peripherals to a Core different from the one selected as "active"? In this case, why is it given the possibility to choose the core (between A9 and M4) in the "Functional group properties"?
How can I fix this? Have I to use two different stand alone configurations, one for the A9 and the other for the M4?
###### EDITED on 2021/02/12 ######
Another thing I notice is that the pin_mux.c and pin_mux.h files generated by the "Config Tool for i.MX" differ from the ones I see in the examples of the FreeRTOS_BSP_1.0.1_iMX6SX. Here there are some pins configuration functions like this one:
void configure_i2c_pins(I2C_Type* base)
{
switch((uint32_t)base)
{
case I2C1_BASE:
// I2C1 iomux configuration
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_SION_MASK;
IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT = IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_DAISY(1);
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_SION_MASK;
IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT = IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_DAISY_MASK;
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_HYS_MASK;
break;
case I2C2_BASE:
// I2C2 iomux configuration
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_SION_MASK;
IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT = IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY(1);
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_SION_MASK;
IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT = IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY(1);
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_HYS_MASK;
break;
case I2C3_BASE:
// I2C3 iomux configuration
IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 = IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(2) |
IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SION_MASK;
IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT = IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY(2);
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 = IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(2) |
IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SION_MASK;
IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT = IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY(2);
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 = IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 = IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_HYS_MASK;
break;
case I2C4_BASE:
// I2C4 iomux configuration
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 = IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE(2) |
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_SION_MASK;
IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT = IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY(2);
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 = IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE(2) |
IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_SION_MASK;
IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT = IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY(2);
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06 = IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_HYS_MASK;
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07 = IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PKE_MASK |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_PUS(2) |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SPEED(2) |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_DSE(6) |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_ODE_SHIFT |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_SRE_MASK |
IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_HYS_MASK;
break;
default:
break;
}
}In the "Config Tool for i.MX" version of the file, instead, initialization are done this way:
/* FUNCTION ************************************************************************************************************
*
* Function Name : BOARD_M4_I2C_InitPins
* Description : Configures pin routing and optionally pin electrical features.
*
* END ****************************************************************************************************************/
void BOARD_M4_I2C_InitPins(void) { /*!< Function assigned for the core: Cortex-M4[cm4] */
// HW_IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_WR(IOMUXC_BASE, 0x00000001u); /* IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT register modification value */
// HW_IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_WR(IOMUXC_BASE, 0x00000001u); /* IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT register modification value */
// HW_IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_WR(IOMUXC_BASE, 0x00000001u); /* IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT register modification value */
// HW_IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_WR(IOMUXC_BASE, 0x00000001u); /* IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT register modification value */
// HW_IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_WR(IOMUXC_BASE, 0x00000002u); /* IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT register modification value */
// HW_IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_WR(IOMUXC_BASE, 0x00000002u); /* IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT register modification value */
// HW_IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_WR(IOMUXC_BASE, 0x00000002u); /* IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT register modification value */
// HW_IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_WR(IOMUXC_BASE, 0x00000002u); /* IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT register modification value */
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_SET(IOMUXC_BASE, 0x00000002u); /* IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 register set mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_CLR(IOMUXC_BASE, 0x0000000Du); /* IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06 register clear mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_SET(IOMUXC_BASE, 0x00000002u); /* IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 register set mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_CLR(IOMUXC_BASE, 0x0000000Du); /* IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07 register clear mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_CLR(IOMUXC_BASE, 0x00000007u); /* IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 register clear mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_CLR(IOMUXC_BASE, 0x00000007u); /* IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 register clear mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_CLR(IOMUXC_BASE, 0x00000007u); /* IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 register clear mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_CLR(IOMUXC_BASE, 0x00000007u); /* IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 register clear mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_SET(IOMUXC_BASE, 0x00000002u); /* IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 register set mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_CLR(IOMUXC_BASE, 0x00000005u); /* IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 register clear mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_SET(IOMUXC_BASE, 0x00000002u); /* IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 register set mask value */
// HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_CLR(IOMUXC_BASE, 0x00000005u); /* IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 register clear mask value */
// Note: The commented code above is generated by the tool in case of simplified register modification using direct values only are needed.
HW_IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_WR(IOMUXC_BASE,
BF_IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_DAISY_GPIO1_IO00_ALT0)); /* Input Select (DAISY) Field: Selecting ALT0 mode of pad GPIO1_IO00 for I2C1_SCL. */
HW_IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_WR(IOMUXC_BASE,
BF_IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_DAISY_GPIO1_IO01_ALT0)); /* Input Select (DAISY) Field: Selecting ALT0 mode of pad GPIO1_IO01 for I2C1_SDA. */
HW_IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_WR(IOMUXC_BASE,
BF_IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_DAISY_GPIO1_IO02_ALT0)); /* Input Select (DAISY) Field: Selecting ALT0 mode of pad GPIO1_IO02 for I2C2_SCL. */
HW_IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_WR(IOMUXC_BASE,
BF_IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_DAISY_GPIO1_IO03_ALT0)); /* Input Select (DAISY) Field: Selecting ALT0 mode of pad GPIO1_IO03 for I2C2_SDA. */
HW_IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_WR(IOMUXC_BASE,
BF_IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_DAISY_KEY_COL4_ALT2)); /* Input Select (DAISY) Field: Selecting ALT2 mode of pad KEY_COL4 for I2C3_SCL. */
HW_IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_WR(IOMUXC_BASE,
BF_IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_DAISY_KEY_ROW4_ALT2)); /* Input Select (DAISY) Field: Selecting ALT2 mode of pad KEY_ROW4 for I2C3_SDA. */
HW_IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_WR(IOMUXC_BASE,
BF_IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_DAISY_CSI_DATA06_ALT2)); /* Input Select (DAISY) Field: Selecting ALT2 mode of pad CSI_DATA06 for I2C4_SCL. */
HW_IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_WR(IOMUXC_BASE,
BF_IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY(BV_IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_DAISY_CSI_DATA07_ALT2)); /* Input Select (DAISY) Field: Selecting ALT2 mode of pad CSI_DATA07 for I2C4_SDA. */
HW_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_WR(IOMUXC_BASE,
BF_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_MUX_MODE_ALT2)); /* MUX Mode Select Field: Select signal I2C4_SCL. */
HW_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_WR(IOMUXC_BASE,
BF_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_MUX_MODE_ALT2)); /* MUX Mode Select Field: Select signal I2C4_SDA. */
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_WR(IOMUXC_BASE,
BF_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_ALT0)); /* MUX Mode Select Field: Select signal I2C1_SCL. */
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_WR(IOMUXC_BASE,
BF_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_MUX_MODE_ALT0)); /* MUX Mode Select Field: Select signal I2C1_SDA. */
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_WR(IOMUXC_BASE,
BF_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_MUX_MODE_ALT0)); /* MUX Mode Select Field: Select signal I2C2_SCL. */
HW_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_WR(IOMUXC_BASE,
BF_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_MUX_MODE_ALT0)); /* MUX Mode Select Field: Select signal I2C2_SDA. */
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_WR(IOMUXC_BASE,
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_MUX_MODE_ALT2)); /* MUX Mode Select Field: Select signal I2C3_SCL. */
HW_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_WR(IOMUXC_BASE,
BF_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE(BV_IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_MUX_MODE_ALT2)); /* MUX Mode Select Field: Select signal I2C3_SDA. */
}I though, perhaps wrongly, that it was enough to overwrite the pin_mux files in my project (the FreeRTOS_BSP_1.0.1_iMX6SX examples in this case).
So, any suggestion how to use them?
