iMX6q ESAI in slave mode, corrupted data, voltage levels?

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iMX6q ESAI in slave mode, corrupted data, voltage levels?

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sfe
Contributor II

Hello!

We're trying to use the ESAI interface on our iMX6q as 8 32bit slot per frame TDM at 96kHz. So with a bit clock of 24.576 MHz. Frame and bitclock are provided by an external codec.

We are able to play a 8ch audio file through aplay. But the data stream just stops for single slots or even several frames. 

On a first try in master mode the whole thing was working. 

We use a 4.1 linux kernel with the latest patches (up to 14-01-2016). So I would have expected some underrun detection in the fsl_esai driver (the check is running but never returns positive). 

On a 8ch file with only one channel with active data I can see the shifting described in errata008000, that is why I would have expected underruns. 

So my questions are:

Is there a differenc in master and slave mode that might explain the data dropouts?

Where can I find out where the bottleneck is? The DMA is burried deeply in the drivers. 

Do you know of any 8ch 96kHz TDM implementations on the iMX6q that work?

Attached you'll find some screenshots. 

Regards,

Sebastian

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sfe
Contributor II

Hello again,

Just to add something to the question.

esai_data_floating Pin_96kHz.png

The Picture shows the analog output signal of the ESAI interface. Date is "FFF0 0000(6x) F0F0" for each frame.

The tx pin is configured as 0x1b070 in the pinctrl in the device tree. That is LOW speed, 40Ohm Drive strength, 100k pull up and hystereses. 

Why does the pin float up like in the picture? Without a data driven out the pin is always at half supply voltage. 

I found something about high impedance stae in the manual. But that only applys in on-demand mode. We are using network mode.

And how can the transmission stop like in the picture when the FIFO never reports an underrun (Register ESAI_SAISR Pin TUE)?

Regards,

Sebastian

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sfe
Contributor II

Ok, we found something.

Currently the Bitclock is connected to ESAI_TX_CLK on Pin ENET_CRS_DV. That pin is in the ENET supply domain and thus at 2.5V.

So we drive the bitclock at 2V5 and see above problems.

When we drive the clocks externally with 3V3 the problems disappear.

Does using the pin as CLK input change something about the internal connections and voltage levels? We could not find anything about that in the manuals. 

What is the recommended use here? And is there an explanation for this?

Regards,

Sebastian

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sfe
Contributor II

Hi Igor,

Thanks for the reply. 

My system already is very bare. 

Running the mmdc test I get:

i.MX6Q detected.
MMDC SUM

MMDC new Profiling results:
***********************
Measure time: 1000ms
Total cycles count: 528096928
Busy cycles count: 86326854
Read accesses count: 334410
Write accesses count: 7010
Read bytes count: 19860996
Write bytes count: 223408
Avg. Read burst size: 59
Avg. Write burst size: 31
Read: 18.94 MB/s / Write: 0.21 MB/s Total: 19.15 MB/s
Utilization: 1%
Bus Load: 16%
Bytes Access: 58

And the read perfomance seems good enough to me.

I checked the DMA settings and changed the TX Watermark from 127 (so almost completely empty) to 64. It did not change anything though. The maxburst parameter did not change anything either. 

Looking at the beginning of a transfer it takes a couple of ms before more the just a few bytes are transmitted at a time. (see attached image). On the right edge it continues as in the pictures above.

esai_data_8ch_96kHz_beginning.png

I will dig into the aplay buffering options. 

But any other advice is highly appreciated.

Regards,

Sebastian

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igorpadykov
NXP TechSupport
NXP TechSupport

Hi Sebastian

there is no difference in master and slave mode.

One can try to test on minimal configuration (without gui),

use mmdc profile tool for measuring ddr loading

MMDC Profiling Tool 

use nxp bsp from

linux-imx.git - i.MX Linux Kernel 

http://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0-LINUX-DOCS&Parent_nodeId=133769948107170617... 

Best regards
igor
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