Hi all,
the DDR3 layout detail in iMX6UL design guide is not clear for me
so I read the IMX6UL 14x14 EVK board file LAY-28617_C2.brd
following table is the DDR3 trace length I extract from Altium
| DRAM_SDCLK0_N | 1474.547 | |
| DRAM_SDCLK0_P | 1478.036 | |
| DRAM_ADDR0 | 1456.372 | |
| DRAM_ADDR1 | 1383.264 | |
| DRAM_ADDR2 | 1383.865 | |
| DRAM_ADDR3 | 1377.21 | minimum |
| DRAM_ADDR4 | 1460.093 | |
| DRAM_ADDR5 | 1385.589 | |
| DRAM_ADDR6 | 1385.052 | |
| DRAM_ADDR7 | 1468.929 | |
| DRAM_ADDR8 | 1456.697 | |
| DRAM_ADDR9 | 1389.506 | |
| DRAM_ADDR10 | 1463.336 | |
| DRAM_ADDR11 | 1455.482 | |
| DRAM_ADDR12 | 1457.502 | |
| DRAM_ADDR13 | 1489.418 | |
| DRAM_ADDR14 | 1381.572 | |
| DRAM_ADDR15 | 1455.742 | |
| DRAM_SDBA0 | 1391.499 | |
| DRAM_SDBA1 | 1378.845 | |
| DRAM_SDBA2 | 1392.906 | |
| DRAM_RAS_B | 1456.112 | |
| DRAM_CAS_B | 1396.785 | |
| DRAM_SDWE_B | 1379.31 | |
| DRAM_CS0_B | 1397.098 | |
| DRAM_CS1_B | 1457.976 | |
| DRAM_SDCKE0 | 1500.327 | maximum |
| DRAM_SDCKE1 | 1475.134 | |
| DRAM_ODT0 | 1388.913 | |
| DRAM_ODT1 | 1456.594 | |
| DRAM_RESET_B | 1394.69 | |
| DRAM_SDQS0_N | 1111.194 | |
| DRAM_SDQS0_P | 1110.196 | |
| DRAM_DQM0 | 992.587 | |
| DRAM_DATA0 | 991.092 | |
| DRAM_DATA1 | 997.784 | |
| DRAM_DATA2 | 998.88 | |
| DRAM_DATA3 | 992.781 | |
| DRAM_DATA4 | 998.4 | |
| DRAM_DATA5 | 998.351 | |
| DRAM_DATA6 | 995.83 | |
| DRAM_DATA7 | 997.645 | |
| DRAM_SDQS1_N | 1024.715 | |
| DRAM_SDQS1_P | 1023.824 | |
| DRAM_DQM1 | 1019.876 | |
| DRAM_DATA8 | 1021.889 | |
| DRAM_DATA9 | 1020.667 | |
| DRAM_DATA10 | 1025.673 | |
| DRAM_DATA11 | 1029.274 | |
| DRAM_DATA12 | 1027.033 | |
| DRAM_DATA13 | 1025.052 | |
| DRAM_DATA14 | 1025.595 | |
| DRAM_DATA15 | 1022.981 |
most of the signals trace length is reasonable
but the SDQS0_P/SDQS0_N is a question ,why they are traced about ~1110 mil?
should they trace to ~1000 mil around?
and following picture is SDQS0_P/SDQS0_N trace, they can be traced to ~1000,
why 1110 mil?
