iMX6Q with 3.10.17 linux kernel and 400MHz DDR clock

[gabrielgrange]

We need to work with 400MHz DDR configuration with a iMX6Q Dual processor. We success to configure pll2 to 396MHz in u-boot thanks to existing forum exchanges (how to change DDR clock of i.mx6)

But linux 3.10.17 kernel hangs when starting :

U-Boot 2014.04-OTG-PR3149_V0.9.9 (Nov 21 2014 - 11:19:24)

CPU:   Freescale i.MX6D rev1.5 at 792 MHz

Reset cause: POR

Board: HCBT_PLUS

I2C:   ready

DRAM:  1 GiB

MMC:   FSL_SDHC: 0

SF: Detected M25P64 with page size 256 Bytes, erase size 64 KiB, total 8 MiB

No panel detected: default to vga-lvds

Display: vga-lvds (640x480)

In:    serial

Out:   serial

Err:   serial

board_late_init(): MFG_BOOT

Net:   using phy at 0

FEC [PRIME], usb_ether

Hit any key to stop autoboot:  0

U-Boot-EVP > clocks

PLL_SYS         792 MHz

PLL_BUS         528 MHz

PLL_OTG         480 MHz

PLL_NET          50 MHz

IPG           49500 kHz

UART          80000 kHz

CSPI          60000 kHz

AHB           99000 kHz

AXI          198000 kHz

DDR          396000 kHz

USDHC1       198000 kHz

USDHC2       198000 kHz

USDHC3       198000 kHz

USDHC4       198000 kHz

EMI SLOW      99000 kHz

IPG PERCLK    49500 kHz

U-Boot-EVP > boot

## Booting kernel from Legacy Image at 12000000 ...

   Image Name:   Linux-3.10.17-OTG-PR3149_V1.0.0

   Image Type:   ARM Linux Kernel Image (uncompressed)

   Data Size:    4911160 Bytes = 4.7 MiB

   Load Address: 10008000

   Entry Point:  10008000

   Verifying Checksum ... OK

## Loading init Ramdisk from Legacy Image at 12c00000 ...

   Image Name:   initramfs

   Image Type:   ARM Linux RAMDisk Image (gzip compressed)

   Data Size:    17238142 Bytes = 16.4 MiB

   Load Address: 00000000

   Entry Point:  00000000

   Verifying Checksum ... OK

## Flattened Device Tree blob at 18000000

   Booting using the fdt blob at 0x18000000

   Loading Kernel Image ... OK

   Loading Ramdisk to 4e4e2000, end 4f55287e ... OK

   Loading Device Tree to 4e4d4000, end 4e4e16fc ... OK

Starting kernel ...

We try to make some changes in busfreq_ddr3.c and ddr3_freq_imx6.S files but we don't find a way to have functionnal kernel with 400Mhz DDR clock.

We also add in our devicetree definition such as :

	soc {
		busfreq { /* BUSFREQ */
			compatible = "fsl,imx6_busfreq";
			clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
			<&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>;
			clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
			"periph_pre", "periph_clk2", "periph_clk2_sel", "osc";
			interrupts = <0 107 0x04>, <0 112 0x4>, <0 113 0x4>, <0 114 0x4>;
			interrupt-names = "irq_busfreq_0", "irq_busfreq_1", "irq_busfreq_2", "irq_busfreq_3";
			fsl,max_ddr_freq = <40000000>;
		};
	};

Our specific DDR initialization is present for information.

Our request is as follow:

  What it the correct way to configure or to stay with 400MHz DDR clock with 3.10.17 (or above) linux kernel ?

Thanks by advance for help you can bring us.

Gabriel GRANGE

Original Attachment has been moved to: iMX6_1066mhz_4x128mx16-centralp_V1.cfg.zip

[igorpadykov]

Hi Gabriel

had you run DDR test (link below) and obtained valid DDR configuration parameters for 400MHz,

also does board run well with DDR frequency 528MHz ?

https://community.freescale.com/docs/DOC-96412

Best regards

igor

[Sasamy · Accepted solution]

Hi Gabriel,

we use 400M as a temporary solution to the problem of stable operation DDR on 528M, possibly in an attachment is not the best solution but it works

Alexander.