iMX6Q PCIE Reference Clock Help

[kcassar]

Hi,

We have designed a custom PCB based around the iMX6Q SabresSD development board.
On the board we require 2 separate 1Gb ethernet interfaces.
We have one up and running fine using the RGMII interface, however we are struggling to get the 2nd one, using I210 on the PCIe interface to work.
The I210 design is a known working design and has been reviewed by Intel. We use the daughterboard in a few of our other products.

On our design we have the i210 connected to the iMX6 without the mPCIe connector.
We have an external 100Mhz clock as we know that the iMX6's PCIe clock is not Gen2 compliant.

In order to prove the interface works, without having to setup the iMX6's PCIe ref clock as an input, I have hardwired a connection to the i210's refclock caps and attempted to get the I210 to come up using the iMX6's refclock.
Unfortunately, our PHY link never comes up. I think this is probably down to the fact the clock lines are connected using mod wire.
I have attached our dmesg just in case anything else jumps out that we may not have set up correctly.

In order to check that it's the mod wire for the clocks causing the problem, I would like to set the iMX6 up to use the external clock as it's lock source.
This is routed on board following the hardware layout design rules.

My question is, how do we go about this?
We have read through a few other posts where people have attempted it but they date back 6/7 years.
What is the simplest way to achieve this without breaking the RGMII interface which I believe uses the same clock source as the PCIe.
Also will this need setting up in Uboot or can we ignore it in uboot and bring it up properly in the Kernal?

Any help with this would be very much appreciated.

Kyle.

[weidong_sun]

Hi,

-----The PCIe clock of i.MX6Q/DL is special. We use CLK1_P/CLK1_N as PCIE_REF_CLK, but CLK1_P/CLK1_N is the LVDS level standard. It cannot be directly connected to the PCIe reference clock of the external device. It must be connected in series with 0.1uF The AC coupling capacitor can be used as PCIE_REF_CLK.

------For the PCIe clock of i.MX6Q/DL, it comes from the PLL6 inside the CPU. If you want to use an external clock, you must bypass PLL6, which will make ENET and SATA unusable. Therefore, we do not recommend using an external PCIE reference clock.

------About CLK1_P/CLK1_N connected to the reference clock of i210.

CLK1_P+0.1uF---->i210_PCIE_REF_CLK+

CLK1_N+0.1uF---->i210_PCIE_REF_CLK-

[Note]

I used the same method to design intel82574IT, also to expand a gigabit network card.

Hope these information is helpful to you.

Have a good day!

Regards,

weidong

[kcassar]

After further testing of the I210 with the SabreSD we have found that the performance of the I210 on Gen1 PCIe is satisfactory.
Because of this we no longer need to change the configuration of the iMX6's clocks.

I have also measured the refclk on the custom board and found that the signal even though hardwired is also as clean as the sabreSD.
The only other thing different on the custom board is that we do not have the load switch to enable the 3V3 to the PCIe.
I was under the impression this was only here to control the allowable load onto the bus.
I am now wondering if this is also here due to sequencing/timing and that maybe this is the reason our phy link never comes up on the custom board.

The 3V3 for the I210 on the custom board comes up at the same time as the 3V3 for the iMX6.

Can anybody tell me if this is likely to be the problem?

Thanks in advance,

Kyle.