iMX6Q : How to work a Watchdog Timer in the on-chip boot ROM code ?

[koichisakagami]

Dear community,
I consider a Watchdog Timer (WDOG) behavior in the on-chip boot ROM code.

In figure 8-2 Serial Download Boot Flow of IMX6DQRM Rev. 3,
it said ARM core will reset if no any activity within 90 seconds when WDOG_ENABLE=1.

Then,
do the WDOG External signals  ( WDOGx_B ,WDOGx_RESET_B_D ) connect to iMX6 I/O pad ?

If Yes,
which pads are connected with WDOG External signals ?

          DISP0_DAT8 or GPIO_9 or SD1_DATA2 or DISP0_DAT9 or GPIO_1 or SD1_DATA3

Best Regards,
       Koichi Sakagami

[koichisakagami]

Dear igor san,

Thank you for your reply.

I got it.

Best Regards

Koichi Sakagami

[igorpadykov · Accepted solution]

Hi Koichi

out of reset state of these pads are described in

Table 100. 21 x 21 mm Functional Contact Assignments i.MX6DQ Datasheet

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

ROM does not configure wdog external signals Upon timeout, the wdog just

asserts the internal system reset signal, WDOG_RESET_B_DEB

to the System Reset Controller (SRC).

Best regards

igor

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