iMX6Q DSI channel clock configuration (HS and LP modes)

[juliocruz]

Hello,

I'm using a MIPI-DSI panel and trying to config the timing modifying the file: mxcfb_hx8369_wvga.c.

I can communicate with the panel controller in LP mode. I can get the status and setup other registers. However, the display don't show anything.

According with the panel controller, the clock period in HS mode must be greater than 4 ns however in the scope is 3sns. So, I think this could be the problem. To change the HS clock period I use the variable "max_phy_clk", however, the LP clock is also changed and I cannot setup the panel register (in LP mode).

Can I change the HS and LP clock independently?

Thanks for any suggestions,

JC

[juliocruz]

Hello community,

I attached a image showing two test case using a MIPI-DSI display with an iMX6Q.

• Case 1: using a clock frequency (according with the variable max_phy_clk included in the file mxcfb_hx8369) of 800Mhz, the LCD setup function is OK. In fact, the communication in command mode with the LCD is great. Later, when the DSI mode change to video (using fb) the frequency clock (in CLKN and CLKP) is bigger than the display specifications. So, I think that this is the problem.
• Case 2: reducing the clk frequency to 400Mhz (again with the variable max_phy_clk), the LCD setup function is not OK. The communication with the display have problems (in command mode).

I would like to change the mipi-dsi driver to adjust a different clock for command mode and another for video mode. However, that's is impossible without the data sheet that explain the DSI module. I didn't find that.

If somebody have other ideas, don't hesitate to share it.

Thanks

JC

[juliocruz · Accepted solution]

I found the MIPI-DSI specifications and figure out the modification. I adjust the register: TX_ESC_CLK_DIVIDSION and now the clock in command mode is OK (independently of the video mode).

[alexreddy]

Hi,

Can anyone suggest me, the procedure for MIPI DSI Host Configuration,

I have a scenario, MIPI DSI Host controller can support/operate at 1Gbps/lane(1000Mbps/lane) & getting the clock of 500MHz on CLKP & CLKN (Bit clock) ,  Had MIPI DSI LCD  HX8260 Can operate at  (480Mbps/lane),

so we need to change/down grade clock at MIPI DSI Host?

Based on the table:

/* configure data for DPHY PLL 27M reference clk out */ static const struct _mipi_dsi_phy_pll_clk mipi_dsi_phy_pll_clk_table[] = {      {1000, 0x74}, /*  950-1000MHz     */      {950,  0x54}, /*  900-950Mhz     */      {900,  0x34}, /*  850-900Mhz     */      {850,  0x14}, /*  800-850MHz     */      {800,  0x32}, /*  750-800MHz     */      {750,  0x12}, /*  700-750Mhz     */      {700,  0x30}, /*  650-700Mhz     */      {650,  0x10}, /*  600-650MHz     */      {600,  0x2e}, /*  550-600MHz     */      {550,  0x0e}, /*  500-550Mhz     */      {500,  0x2c}, /*  450-500Mhz     */      {450,  0x0c}, /*  400-450MHz     */      {400,  0x4a}, /*  360-400MHz     */      {360,  0x2a}, /*  330-360Mhz     */      {330,  0x48}, /*  300-330Mhz     */      {300,  0x28}, /*  270-300MHz     */      {270,  0x08}, /*  250-270MHz     */      {250,  0x46}, /*  240-250Mhz     */      {240,  0x26}, /*  210-240Mhz     */      {210,  0x06}, /*  200-210MHz     */      {200,  0x44}, /*  180-200MHz     */      {180,  0x24}, /*  160-180MHz     */      {160,  0x04}, /*  150-160MHz     */ };

Horizontal Parameters
Parameter	Symbol	Value	Units
Horizontal Sync/ Horizontal Low pulse width	HS	24	DCK
Horizontal Back porch	HBP	24	DCK
Horizontal Front Porch	HFP	72	DCK
Horizontal Active Area	HDISP	800	DCK
Total Clocks per line		920	Clocks/line

Vertical Parameters
Parameter	Symbol	Value	Units
Vertical Sync/ Vertical Low pulse width	VS	2	Line(s)
Vertical Back porch	VBP	10	Line(s)
Vertical Front Porch	VFP	12	Line(s)
Vertical Active Area	VDISP	1280	Line(s)
Lines per frame		1304	Line(s)/frame

Q) We need to configure the DSI Pixel clock , Polarity on MIPI DSI Host side? (correct me if I am wrong)

Q) we have 3 type of video modes [Video with Burst, Non Burst with Pulses, Non burst with Event sync] in MIPI DSI Host.

Q) How do we configure for Non burst with Event Sync in i.MX6, MIPI DSI Host.

Please anyone review and and let me know the procedure is correct or not , Please provide your inputs,