On our board we have connected CCM_CLKO1 to MCLK on our audio codec and need to generate a 11.2896 MHz frequency. The clock to be generated on CCM_CLK01 is pll4_main_clk and all this has been setup in our dts (see below). When dumping the clock tree from within Linux all seem to be correctly setup, but when measuring the output on CLK01 I get double the frequency (~22 MHz). If anyone has input (preferably a solution) on this issue I would appreciate it.
PLL4 clock tree
in Linux (/sys/kernel/debug/clk/clk_summary)
pll4_bypass_src 1 1 24000000 0 0
pll4 1 1 722534400 0 0
pll4_bypass 1 1 722534400 0 0
pll4_audio 1 1 722534400 0 0
pll4_post_div 1 1 180633600 0 0
pll4_audio_div 1 1 90316800 0 0
ssi2_sel 0 0 90316800 0 0
ssi2_pred 0 0 22579200 0 0
ssi2_podf 0 0 11289600 0 0
ssi2 0 0 11289600 0 0
cko1_sel 1 1 90316800 0 0
cko1_podf 1 1 11289600 0 0
cko1 1 1 11289600 0 0
cko 2 2 11289600 0 0
DTS, assign CKO to PLL4 audio div
...
assigned-clocks = <&clks IMX6QDL_CLK_CKO>, <&clks IMX6QDL_CLK_CKO1_SEL>;
assigned-clock-parents = <&clks IMX6QDL_CLK_CKO1>, <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <11289600>, <0>;
...
DTS, set PLL4 audio div clock rate
The maximum divider for CLKO1 is 8 (see ref.man rev4 ch 18.6.21) so the clock rate of the parent PLL4 audio div is set to 8x11289600=90316800
&clks {
assigned-clocks = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <90316800>;
};PLL4 audio div is not documented in reference manual
Looking at the code I can see that the divider for PLL4_AUDIO_DIV is set to be bit 15 in CCM_ANALOG_MISC register (0x020C8170)
You can see the code below (please note that I don't use community Linux. I have just included the link below since community Linux is on GitHub).
linux-fslc/clk-imx6q.c at 4.1-2.0.x-imx · Freescale/linux-fslc · GitHub
In the reference manual bit 15 is set to be reserved (chapter 18.7.20, rev 4). The revision history of the document (chapter B.1.19) says that MSB:LSB has been removed from the register. It seems as though the Linux code hasn't been updated to reflect this change in the manual. Is it okay to use this divider?
Old post about same issue
I found an old post describing a similar issue, but a solution wasn't presented.
https://community.nxp.com/thread/355327
Summary
- Want 11.289600 MHz on CCM_CLKO1, but gets double the frequency (~22 MHz)
- The clock to be generated on CLKO1 is pll4_main_clk
- Kernel used: 4.1.15_2.0.0
- Processor: iMX6 Quad
