In my application, i have two DDR3( 2x 1Gbx16) interfaced to iMX6D. Fly by topology is used for better SI. Any freescale recommendation for parallel termination resistor value ? Does series termination required for DDR3 interface of iMX6D? If so, what is the optimum value?
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You may try the fly-by for 2 parts, using general recommendations of
Chapter 3 (i.MX 6 Series Layout Recommendations) in "Hardware Development Guide
for i.MX 6 ...". Next, simulation should be provided to define termination resistors.
Also, let me remind, DDR calibration must be provided for such topology.
"i.MX 6 Series DDR Calibration"
< http://cache.freescale.com/files/32bit/doc/app_note/AN4467.pdf >
According to the i.MX6 Design Checklist, it is suggested to use "T" topology
when the number of DDR3 chips are not more than four. Otherwise "Fly-by"
Topology is recommended, since it allows to decrease timing / trace length
requirements because of additional calibration procedures.
Is there any issue when i use Fly by topology for 2 DDR3 ? I have checked hardware user guide and design checklist of iMX6D. Nowhere it is mentioned fly-by is not recommended for less than 2 chips.
Also, i have seen that DDR3 is built for Fly-by routing...
You may try the fly-by for 2 parts, using general recommendations of
Chapter 3 (i.MX 6 Series Layout Recommendations) in "Hardware Development Guide
for i.MX 6 ...". Next, simulation should be provided to define termination resistors.
Also, let me remind, DDR calibration must be provided for such topology.
"i.MX 6 Series DDR Calibration"
< http://cache.freescale.com/files/32bit/doc/app_note/AN4467.pdf >
Is there any recommendations for the resistor values when i opt fly-by?