iMX6 SoloX passing data from M4 to A9

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iMX6 SoloX passing data from M4 to A9

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Contributor III

I’m working on a project using the iMX6 SoloX . The M4 core gathers data and feeds it to the A9 core for display. The data points coming into the M4 come asynchronously to each other and are passed upstream as a single 32-bit value. As some of the values are read several times per second, this means that ~ 200 values/second get passed to the A9. The usual way to pass data between processors is to use the MU. The problem with this is that each message results in an interrupt to the A9 with the accompanying context switching just to pass one 32-bit value.

I’m exploring the possibility of using a form of shared memory that both processors can access without using the MU. Two potential issues exist with this method: the A9 and the M4 trying to access the same location at the same time, and cache/data coherency.

What will happen if both cores try to access the same memory location at the same time; is there a bus arbitrator that prevents a problem? Would it generate a bus fault? In this project, the M4 always write to the location (never reads) and the A9 only reads. Also it is not important that the A9 get the very latest data from a location as the values on the screen get updated ~15 times/sec. There is no control done with the data; only monitoring. Just trying to see if this system would work (especially without using a mutex).

For the second issue on caches, the M4 could of course due a dcache flush line every time it writes, and the A9 do a dcache invalidate line to get the latest data from memory. This takes time and bus bandwidth. I know that the A9 has a snoop control unit (SCU) which keeps the A9 cache current when using DMA devices. Does this also work between the A9 and M4 – will it ensure coherency of data between the A9 and M4?

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Contributor III

Thanks for the reply. Is there a way to download the imx6sx bare metal SDK (or is there one? I don't see any download button at the source in GitHub.

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NXP TechSupport
NXP TechSupport

1.1.0_iMX6_Platform_SDK.zip can be obtained from    SMP Enable in IMX6 

i.MX6SoloX core/caches (except M4) are similar to i.MX6DQ.

For M4 examples one can look at FreeRTOS_MX6SX_1.0.1_LINUX

available on

i.MX 6SoloX Applications Processors | Arm® Cortex®-A9, Cortex-M4 | NXP 

Best regards
igor

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Contributor III

Thanks for your response. The real question is how can a section of memory be set up to be accessible to two (or more) cores to create a shared memory. In my case (using the iMX6SX, neither core (A9 or M4) is using Linux so I'm not tied down to the requirements of trying to work around what Linux will let you do. The issue is how to set up the caches and mmu to create a shared section of memory.

In my case, I don't need to pass very many values and the values are atomic. Therefore I decided to use the LUT table of the (unused) second QSPI controller. It makes a great sharable area that is not cached. However it would be nice to know how to do it correctly using standard DDR RAM.

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NXP TechSupport
NXP TechSupport

for non- linux examples one can look at baremetal sdk:

rt-thread/armv7_cache.c at master · RT-Thread/rt-thread · GitHub 

and various cache errata listed in Chip Errata for the i.MX 6SoloX Applications Processor - IMX6SXCE

Best regards
igor

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NXP TechSupport
NXP TechSupport

Hi Ken

>What will happen if both cores try to access the same memory location at the

>same time; is there a bus arbitrator that prevents a problem?

yes there is bus arbiter.

For data sharing between cores one can check suggestions on

i.MX7D: How to share >100KiB of data between A7 and M4 all at once? 

https://community.nxp.com/docs/DOC-335105 

Best regards
igor
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