iMX6 Solo DDR3 byte address troubleshoot

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

iMX6 Solo DDR3 byte address troubleshoot

Jump to solution
1,475 Views
andreaskarlsson
Contributor III

Hi,

I've a question regarding an iMX6Solo issue, we've used the DDR3 Script Aid XLS to create a basic configuration(no stress test calibration run). We've used the result and converted to Lauterbach CMM syntax, so far so good. But when the iMX is reset and started with the resulting values we get a weird phenomenon, Byte[1] gets written at address +8 for some reason.

Example

Data.Set 0x10000000 %Long 0xFFFFFFFF results in ,

0x10000000 = 0xFF00FFFF

<snippet>

0x10000008 = 0x00FF0000

The DDR3 is connected:

CPU                                Micron2Gb         Micron2Gb

A[0:15]  <->                     A[0:15]<->      A[0:15]

D[0-7 swapped] <->          D[0-7]

D[8-15 swapped]<->         D[8-15]

D[16-23 swapped]<->                             D[0-7]

D[24-31swapped]<->                             D[8-15]

However we didn't connect the byte(s) low bits,so write levelling will not function, but I would expect the DDR3 Script Aid XLS to generate a valid configuration regardless if write levelling can be used or not?

Attached is the Script Aid input.

regards

Andreas

Labels (2)
Tags (1)
0 Kudos
Reply
1 Solution
1,169 Views
andreaskarlsson
Contributor III

We got it to work, basically

1. The values DDR3 Script Aid didn't work AS IS, it was required to run DQS Gate,Read and Write calibration.

View solution in original post

0 Kudos
Reply
3 Replies
1,169 Views
Yuri
NXP Employee
NXP Employee

  Please look at some hints below

1.

  Please double check the schematic regarding DDR signal connections.

2.

  Please check PCB design regarding DDR signals, using Chapter 3 (i.MX 6 Series
Layout Recommendations) of the “Hardware Development Guide for i.MX 6Quad,
6Dual, 6DualLite, 6Solo Families …”


http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf

In particular, please use to Excel page named “MX6 DRAM Bus Length Check” in
“HW Design Checking List for i.Mx6”, linked below.

https://community.freescale.com/docs/DOC-93819


Have a great day,
Yuri

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

0 Kudos
Reply
1,169 Views
andreaskarlsson
Contributor III

Thank you for answer, we'll look into above pointers.

One question though: If DDR3 Script Aid input values is correct, will the output configuration run if it is used without modification? At the moment we're unable to run the stress test due to using UART5.

regards

Andreas

0 Kudos
Reply
1,170 Views
andreaskarlsson
Contributor III

We got it to work, basically

1. The values DDR3 Script Aid didn't work AS IS, it was required to run DQS Gate,Read and Write calibration.

0 Kudos
Reply