iMX6 SPI controller slave mode burst length

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iMX6 SPI controller slave mode burst length

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BillHegardt
Contributor II

When configured for slave mode, my testing indicates that it ignores the burst length and always transfers 32-bits to/from the FIFO. I notice the manual only mentions master mode when it talks about the burst length.

Is this by design?  Anyone have it working for 1 byte per word?

I set the burst length to 7 (8 - 1) so the control register was loaded with 0x0070e301 and the cfg register with 0. I load the FIFO with 1 byte per word. On a scope I see each byte sent followed by 3 zero bytes. I expect to see the bytes sent consecutively.

Works great with 32-bits per word other than the known SS termination issue.

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vg53
Contributor I

Hi @Yuri .

We want to use iMX8 SPI in slave mode. We need to transfer a 64 byte packet every 32 us. Do I understand correctly I can set the burst length to 64*8-1=511, lower SS line, send all 512 bits, and then set SS line to high? In the manual, they say the data transfer to FIFO upon the positive edge of SS, so I thought I could transfer only 32 bits in a burst in a slave mode.

Thank you 

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Yuri
NXP Employee
NXP Employee

@vg53 
Hello,

  Yes, it is needed to set the burst length to 64*8-1=511, lower SS line, send all 512 bits, and then set SS line to high. 

   Note: SS is asserted / negated by SPI master. SPI slave can only analyze this signal.

Regards,
Yuri.

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BillHegardt
Contributor II

Commenting on my own post.

I notice the Linux driver in the BSP (master mode only) configures the burst length to be the number of bits per word, but the response I received from tech. support case #00163683 leads me to believe that the burst length should be set to the number of bits in the entire transfer (at least in slave mode). If that's true, then burst length has a different definitions in master and slave mode -or- the Linux BSP should not be configuring it as bits per word -or- I'm very confused.

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Yuri
NXP Employee
NXP Employee

Hello,

  For the slave mode the maximum length of the single SPI burst is defined by FIFO size

or SS negation. But due to errata ERR009535, the slave must configure the burst length

to match the total number of bits sent by the master in a single transfer (burst). 

Regards,

Yuri.

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Yavuz
Contributor III

Hi,

@Yuri  how to configure the burst length ? 

Regards. 

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Yuri
NXP Employee
NXP Employee

@Yavuz 
Hello,

   from the erratum:
Slave mode with unspecified burst length cannot be supported due to this issue. The burst length
should always be specified with the BURST_LENGTH parameter and the SS_CTL[x] should be
set to zero.
  There is no workaround except for not using the SS_CTL[x] = 1 option in the Slave mode. The
accurate burst length should always be specified using the BURST_LENGTH parameter 

Regards,
Yuri.

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Yavuz
Contributor III

Hi @Yuri ,

I see that the BURST_LENGTH parameter is bits 20-32 on CONTROL REGISTER for IMX6dl

Thank you. 

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