iMX6 Quad Local Timer

[ogj]

I want to use the local timer in one of the cores to create a "tick" timer. According to what I've read in various manuals, each of the cores in the iMX6 Quad has a private timer that can be used for my application. My understanding is that each of these timers will have the same bus address (for ease of SW)  but the timer will only respond to the core it belongs to; kind of like a private address within the core.

My problem is that there is not a lot of information about these timers. I believe that the address of the timer starts at 0x00A00600 - is this correct? I believe the register structure is:  

// LOCTMR - Peripheral register structure
typedef struct LOCTMR_MemMap
{
   uint32_t LDVAL;               //counter reload value      offset 0x000
   uint32_t CNTR;                //count reg                 offset 0x004
   uint32_t CNTL;                //control reg               offset 0x008
   uint32_t INTSTS;              //interrupt status reg      offset 0x00C
} volatile *LOCTMR_MemMapPtr;

Is the above information correct? I have been unable to find what the interrupt vector is - where do I find it?

[ogj]

For anyone following this and doing a bare metal application, the above interrupt vectors are wrong. The Reset, Undefined, SVC, Prefetch, Data Abort, IRQ, and FIQ interrupts are vectored by the VBR. GIC vectors are as follows:

0 - 16    Software generated interrupts

16 - 26  Not used

27, 28   Not sure

29       Local timer

30, 31   Not sure

32 - 159   See Table 3-1 in the RM (as of Rev 5, 6/18)

The base address of the local timer is in fact 0x00A00600. The register set for controlling it as given above are correct. The bit definitions in the Control Register are:

// Bit definitions for the Control Register
#define LOCTMR_CNTL_TMRENB 0x00000001 //timer enable
#define LOCTMR_CNTL_AUTORL 0x00000002 //auto reload
#define LOCTMR_CNTL_IRQENB 0x00000004 //interrupt enable
#define LOCTMR_CNTL_PRESCL_MASK 0x0000FF00 //controller prescaler mask

Note that the counter as is is a down counter. Does anyone know if there is a bit in the Control Register to change to an up counter?

[Yuri]

Hello,

  i.MX6 Reference Manual (RM) in Table 2-1 (System memory map) provides address section

from 0x00A0_0000 till  0x00A0_1FFF  for  ARM MP resources, where Global and Private
timers may be found. Use ARM documentation for more details about the timers.

ARM Information Center 

  According to section 3.2 (Cortex A9 interrupts) of the i.MX6 RM:
"The Global Interrupt Controller (GIC) collects up to 128 interrupt requests from all chip
sources and provides an interface to the Cortex A9 CPU cores. The first 32 interrupts are
private to the CPUs' interface. These interrupts are not included in the table below. All
interrupts besides those private to the CPU are hooked up to the GPC."

Regards,

Yuri.

[ogj]

I saw Table 2-1, that's where I got the 0x00A00600 from. However the entry for Table 2-1 for the range 00A0_0000 to 00A0_1FFF says private timers and watchdogs, so there's more than just one timer in there. What's the address of the local timer? Also I know that the first 32 interrupts are private to each of the cores. Here's what I know so far:

// GIC Interrupt Number Definitions
typedef enum
{
   A9_Reset                     = 0,                // Reset (Hardware Interrupt)
   A9_UndefinedInstruction      = 1,                // Undefined Instruction (Hardware Interrupt)
   A9_SupervisorCall            = 2,                // Supervisor Call (Hardware Interrupt)
   A9_PrefetchAbort             = 3,                // Prefetch Abort (Hardware Interrupt)
   A9_DataAbort                 = 4,                // Data Abort (Hardware Interrupt)
   A9_Reserved5                 = 5,                // Reserved (Hardware Interrupt)
   A9_IRQ                       = 6,                // IRQ (Hardware Interrupt)
   A9_FIRQ                      = 7,                // Fast IRQ (Hardware Interrupt)
   A9_Reserved8                 = 8,                // Reserved (Hardware Interrupt)
   A9_Reserved9                 = 9,                // Reserved (Hardware Interrupt)
   A9_Reserved10                = 10,               // Reserved (Hardware Interrupt)
   A9_Reserved11                = 11,               // Reserved (Hardware Interrupt)
   A9_Reserved12                = 12,               // Reserved (Hardware Interrupt)
   A9_Reserved13                = 13,               // Reserved (Hardware Interrupt)
   A9_Reserved14                = 14,               // Reserved (Hardware Interrupt)
   A9_Reserved15                = 15,               // Reserved (Hardware Interrupt)
   GIC_SGI0                     = 16,               // Software Generated Interrupt
   GIC_SGI1                     = 17,               // Software Generated Interrupt
   GIC_SGI2                     = 18,               // Software Generated Interrupt
   GIC_SGI3                     = 19,               // Software Generated Interrupt
   GIC_SGI4                     = 20,               // Software Generated Interrupt
   GIC_SGI5                     = 21,               // Software Generated Interrupt
   GIC_SGI6                     = 22,               // Software Generated Interrupt
   GIC_SGI7                     = 23,               // Software Generated Interrupt
   GIC_SGI8                     = 24,               // Software Generated Interrupt
   GIC_SGI9                     = 25,               // Software Generated Interrupt
   GIC_SGI10                    = 26,               // Software Generated Interrupt
   GIC_SGI11                    = 27,               // Software Generated Interrupt
   GIC_SGI12                    = 28,               // Software Generated Interrupt
   GIC_SGI13                    = 29,               // Software Generated Interrupt
   GIC_SGI14                    = 30,               // Software Generated Interrupt
   GIC_SGI15                    = 31,               // Software Generated Interrupt
   GIC_IOMUXC                   = 32,               // Private Peripheral Interrupt
   GIC_DAP                      = 33,               // Private Peripheral Interrupt
   GIC_SDMA                     = 34,               // Private Peripheral Interrupt
   GIC_VPU_JPG                  = 35,               // JPEG codec interrupt
   GIC_SVNS                     = 36,               // PMIC power off request
   GIC_IPU                      = 37,               // IPU error interrupt
 

So I figure that the timer interrupt is between 8-15 but which one? I'd also like to verify that my understanding of the local timer register set is correct. Anyone know?

[ogj]

Anyone have an answer to what is the address of the register set for the local timer and what is the interrupt vector?