iMX6 PCIe MSI doesn't trigger ARM interrupt.

[brentjosefiak]

Hello,

I am attempting to integrate a PCIe peripheral configured as an EP with the mx6 configured as a RC.  Initial configuration goes well, and the device is able to read/write into the mx6's memory space once it has been granted bus mastering.  Unfortunately the device has been unable to trigger an ARM interrupt when signaling a MSI.

The EP has had its MSI's enabled and allocated (8 of them EP 0, MSI 0-7), both the MX6 and EP share the same MSIC address, the MSIC enable bits are set and the MSIC mask is cleared.  An interrupt handler is attached to IRQ 152.

My program dumps the MSIC mask and status before and after the test:

0[0x1ffc82c 0x1ffc830]:current mask:0x0 status:0x0

<EP writes MSI>

0[0x1ffc82c 0x1ffc830]:current mask:0x0 status:0x1

At this point no ARM interrupt is triggered, despite the fact that the status bit is asserted.

I've manually inspected the ARM GIC and confirmed that IRQ 152's ISENABLERn bit is asserted.  To test my ISR routine I've manually set the ISPENDRn register and successfully triggered the handler.

What could cause an asserted MSI status bit to not trigger the ARM GIC?

Is there a way to check the state of msi_ctrl_int ?

Thanks,

Brent

[iqrajaved]

Hi, 

Have you solved the problem?

I am facing issue in the reception of the MSI interrupt in RC driver. I have set the controller address register as well as the MSI Address registers of capabilities with 0x01FF8000. The inbound region to receive MI MWr TLP is set as follow:

iATU_struct.iATUVR =  (1<<31); /* InBound region 0*/

iATU_struct.iATURLTA = (UINT32) 0x4F80000;

iATU_struct.iATURUTA = 0;

iATU_struct.iATURC1 = 0; /* type of region memory */ 4

iATU_struct.iATURC2 = (1 << 31) | (1 << 30); /* Enable ATU and BAR match mode */

I am writing 0x0000 in the MSI data reister of capabilities (EP# = 0 and interrupt # = 1). The Int_enable0 register is 0xFF and Int_mask0 register is set as 0x0. But I am receiving no interrupt of MSI. 

What should be the reason?

Thank you,

Iqra Javed

[iqrajaved]

NXP community, can anyone guide me regarding this issue? 

Why I am unable to receive MSI interrupt?

[YixingKong]

Brent

This discussion is closed since no activity. If you still need help, please feel free to reply with an update to this discussion, or create another discussion.

Thanks,

Yixing

[YixingKong]

Brent

Had your issue got resolved? If yes, we are going to close the discussion in 3 days. If you still need help, please feel free to reply with an update to this discussion.

Thanks,
Yixing

[GordyCarlson]

As part of Brents effort to find a SW template that illustrates PCIe MSI operation....I read Pete Pinewski's recent FAE community thread that provided the latest Linux patches to enable MSI, as the previous Freescale Linux BSP did not support MSI.  We would like to get the source code for these patches so we can compare them  (and the interrupt init/handling) with the customer's code, which will ultimately run on a QNX OS.   Brent pulled the imx_3.0.35_4.1.0 zip file from our Freescale site but was unable to find it listed in the tags from the git repo.  Is there a recommended arch/arm/configs to enable PCIe and MSIs?

-Gordy

Freescale FAE

supporting this customer