iMX6 IPU1 DISP1 and other things

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iMX6 IPU1 DISP1 and other things

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adrianthewlis
Contributor III

I must admit, the more I read the iMX6DQ manual, the more confused I get! I would love a tutorial or a diagram that explains it all, but failing that here are some specific questions:

1) Are the IPU1_DISP1 pins associated with IPU1_DI1? Do I need to send the data to DI1 to get the signals out of DISP1?

2) Assuming the above is true. If I am only using DISP1/DI1 and not DISP0/DI0, would the data be primary flow or secondary flow? Which DMA channel is used?

3) The IDMAC has 50 channels, all with specific functions. The DC has 10 channels... what are they, and do they have specific functions? The SDK uses Channel5 for RGB output to DISP0... would I use something different for DISP1?

4) The DC doc. refers to 4 displays. In the SDK Display#2 is used for the RGB output. However changing that value to 0,1 or 3 seems to have no effect. What is the significance of the display number?

Thanks!

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igorpadykov
NXP Employee
NXP Employee

Hi Adrian

1. yes

2. according to Figure 37-2. IPU Detailed Block Diagram

i.MX6DQ Reference Manual (rev.3  7/2015), DISP0/DI0 are associated with primary

and DISP1/DI1 with secondary display

3. all IDMAC description is given in RM, Table 37-10 shows channels specific for

primary and secondary flows.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

As additional reading also one can refer to

A Deep Dive into Image Processing for i.MX 6 Series Applications Processors

2. for writing code for different IPU and DI number one needs to change codes

appropriately, including sync (VSYNC,HSYNC) generators, DRDY/DV, IPUx_DIx_D0_CS,

they are assigned to IPUx different pins given in Table 68. Video Signal Cross-Reference

i.MX6DQ Datasheet (rev.4, 7/2015)

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

Sync (VSYNC,HSYNC) generators are programmed using sect.37.4.10.3

Timing generator RM.

Regarding SDK Display#2, seems SDK has codes only for LCDs available for reference boards:

Hannstar LVDS, MIPI lcd, e.t.c., so ID selects one of these lcds, not IPU DI port.

Best regards

igor

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igorpadykov
NXP Employee
NXP Employee

Hi Adrian

1. yes

2. according to Figure 37-2. IPU Detailed Block Diagram

i.MX6DQ Reference Manual (rev.3  7/2015), DISP0/DI0 are associated with primary

and DISP1/DI1 with secondary display

3. all IDMAC description is given in RM, Table 37-10 shows channels specific for

primary and secondary flows.

http://cache.freescale.com/files/32bit/doc/ref_manual/IMX6DQRM.pdf

As additional reading also one can refer to

A Deep Dive into Image Processing for i.MX 6 Series Applications Processors

2. for writing code for different IPU and DI number one needs to change codes

appropriately, including sync (VSYNC,HSYNC) generators, DRDY/DV, IPUx_DIx_D0_CS,

they are assigned to IPUx different pins given in Table 68. Video Signal Cross-Reference

i.MX6DQ Datasheet (rev.4, 7/2015)

http://cache.freescale.com/files/32bit/doc/data_sheet/IMX6DQCEC.pdf

Sync (VSYNC,HSYNC) generators are programmed using sect.37.4.10.3

Timing generator RM.

Regarding SDK Display#2, seems SDK has codes only for LCDs available for reference boards:

Hannstar LVDS, MIPI lcd, e.t.c., so ID selects one of these lcds, not IPU DI port.

Best regards

igor

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. Thank you!

-----------------------------------------------------------------------------------------------------------------------

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adrianthewlis
Contributor III

Igor,

As a sanity test, I am running the SDK LCD example on the Freescale SDB board. I have verified that the DISP0 signals come out on the DISP0 port.

In the SDK sample code, in ipu_display_setup() I change di from 0 to 1, and changed channel to MEM_TO_DP_FG_CH27. The IOMUX for the DI1 pins are set as ALT1:

     EIM_ADDR16 - PCLK

     EIM_AD12 - VSync

     EIM_AD11 - HSync

     EIM_AD10 - DE

     (all the other IPU1_DISP1 pins are setup as well)

As far as my understanding goes, this SHOULD be sufficient to switch the output from DISP0 to DISP1.

However the DI1 pins are just set at 3.3V, and the data pins seem to be floating at strange levels (0.4V). If I drive the pins manually, they all work fine... so I have the correct pins, and they aren't connected to anything else that would drive them.

I assume either I have mis-understood something key, or the SDK code is incomplete/incorrect.

Thanks.

Adrian

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igorpadykov
NXP Employee
NXP Employee

Hi Adrian

SDK was verified only with configurations available

on reference boards: none uses IPU1_DISP1 pins.

Also SDK is not supported and provided just as reference code

for better understanding of hardware.

In general IPU1_DISP1 pins are used in i.MX51 EVK Linux (IPU is similar to i.MX6)

one can look at:

i.MX51 Evaluation Kit|Freescale

Board Support Packages (8)

IMX51 SDK LINUX BSP Validation Tests (REV 2009.12)

Linux 2.6.35 Source Code Files 2010.11 for i.MX51. Engineering Release (REV ER2010.11)

or uboot splashscreen

https://boundarydevices.com/u-boot-display-support-on-i-mx51/

Best regards

igor

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adrianthewlis
Contributor III

Igor,

Okay I finally found it. In the function ipu_enable_display() DI1 is NOT ENABLED!

With that fixed, all that was needed was to change the DI specified from 0 to 1.

Upside: I have learned a lot more about the functioning of the IPU much sooner.

Downside: Wasted a week.

Please pass on this information to whoever is in charge of the SDK, and make sure its fixed for the next release. This has been a VERY expensive exercise for me.

Many thanks again for all you help... with nothing working for this long, I must have sounded like an idiot... thanks for you patience.

God bless.

Adrian

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adrianthewlis
Contributor III

Igor,

Thanks so much this is very helpful. The Deep Dive" is another great resource.

I hope you don't mind if I clarify something with you:

To send data to the secondary screen (DISP1) would I use IDMAC channel #27 (the primary flow of the auxiliary plane) or #24 (the secondary flow of the main plane)? My "guess" is #27 because it is SYNC, but the DMFC/DC numbering of 5F/5 makes me unsure.

The nomenclature is a little ambiguous.

I have written drivers for a number of chipsets over the years... but this is definitely the most complex!

Many thanks.

Adrian

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