iMX6 GIC Documentation

[ogj]

I would like some verification on my understanding of exception handling in the Cortex A (specifically the iMX6 A9) architecture. It appears that exceptions can be divided into two categories. The first group (reset, undef, svc, prefetch, abort, irq, and firq) are part of every ARM architecture, and in the Cortex A they can be located starting at either 0x00000000, 0xFFFF0000 depending on the V bit in the SCTLR. It appears most OS's set the V bit so the vectors are in high memory. For instance, location 0xFFFF0004 holds an instruction such that when this exception occurs, the instruction at that address is executed. The most common instruction used is LDR  PC, #offset.

All other interrupts appear to run through the GIC. There is a little discussion in section 12.2 of the ARM Cortex A Programmer's Guide, but nothing on how to program it (registers, bits in registers, etc.). This is what I'm trying to find. Where is the documentation for the GIC? Nothing in the RM or the ARM Cortex A9 Technical Reference Manual. I can dig a few things out of the BSP code, but I would still like some documentation.

For instance, if the address of the reset, undef, … vector table is fixed at 0x0000_0000 or 0xFFFF_0000 (and the core knows where it is by the V bit), what is loaded into the VBAR and how is the value determined?

Thanks for your help.

[Sporty_b]

Hey guys,

thank for your usefull informations so far.
I'm struggeling with a similar topic and after searching around all the forums and diving into various documentations I found the register for VBAR:

https://developer.arm.com/documentation/ddi0388/f/System-Control/Register-descriptions/CP15-c12-regi...

As the VBAR is defined in the coprocessor, it can't be found in the RM of the imx6 I guess. It took me quite a while to figure out what is documented where and im still not sure about it.
Please correct me if I'm wrong...

One question I still haven't clarified is, of the VBAR definition is unique for each core on multicore architectures, or if once set for all cores. As I'm trying to run an AMP setup, this is an essential question for me.

Thanks again, looking forward to your reply if the topic is still on for you.

[ogj]

Actually the best reference I found is the iMX 6 Series Firmware Guide (IMX6FG). It has a good chapter on using the GIC. Luckily I found a link in an email from years. The link was to Rev 0 11/2012. Is this still valid or is there a newer version?

[ogj]

Thank you for your response. I finally did find the ARM Generic Interrupt Controller spec (v2) and the CoreLink GIC-400 Generic Interrupt Controller TM (Rev r0p1). I still have a few questions:

If the address of the reset, undef, … vector table is fixed at 0x0000_0000 or 0xFFFF_0000 (and the core knows where it is by the V bit), what is loaded into the VBAR and how is the value determined?

On the imx6dl it appears that DDR memory starts at 0x1000_0000 and on the board I'm using there is 1GB - so it runs to 0x5000_0000. There's obviously no memory at 0xFFFF_0000, so do I need to map some memory (64KB) to cover that? Can both cores use the same code that I put there?

Which register steers a given interrupt to one core or the other?

Thanks again for your help

[igorpadykov]

Hi Ken

gic description can be found in arm resources

ARM Generic Interrupt Controller Architecture version 2.0 - Architecture Specification | ARM Generic... 

i.MX6DQ gic examples can be found in sdk (1.1.0_iMX6_Platform_SDK.zip) found on

SMP Enable in IMX6 

Please look at Chapter 4 Configuring the GIC Driver  iMX6_Firmware_Guide.pdf  included in package

Best regards
igor
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