iMX6 EPIT Clock Source

[MichaelV]

Hi,

The EPIT clock source (EPITx_CR:CLKSRC) option 2 (0x10) is the high frequency clock. Am I right to assume this is the 24 MHz CKIH clock source?

I'm a bit confused by the description of this clock source. In Table 25-2 it states:

Clock name        Clock root       Description

ipg_clk_highfreq  perclk_clk_root  High-frequency reference clock

But what has ipg_clk_highfreq to do with the perclk_clk_root? And if this is really the perclk, then I'm confused because the perclk derives from the ipg_clk (see the Clock Tree diagram), so what then is the difference between CLKSRC selection 1 and 2?

[igorpadykov]

Hi Michel

this clock is perclk_clk_root, depicted on

Figure 18-2. Clock Tree - Part 1  i.MX6

IMX6SDLRM

i.MX 6Solo/6DualLite Applications Processor Reference Manual.

ipg_clk is another clock  ipg_clk_root peripheral clock,

difference in divider CSCMR1[PERCLK_PODF]

Best regards

chip

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[MichaelV]

I'm confused. The RM states:

High-frequency reference clock (ipg_clk_highfreq)

This clock is provided by the Clock Control Module (CCM). This clock remains on

during low-power mode when the peripheral clock is turned off, allowing EPIT to

use this clock in low-power mode. In normal mode, the CCM synchronizes this clock

to ahb_clk; in low-power mode, CCM switches to an unsynchronized version.

Which signal is the peripheral clock mentioned above? If you look at the clock tree, you'll see that the PERCLK derives from the IPG clock. The RM states:

Peripheral clock (ipg_clk)

This is the peripheral clock (PER Clock) which is provided (and optionally gated) by

the CCM. This clock is typically used in normal operations. In low-power modes, if

the EPIT is programmed to be disabled (via STOPEN or WAITEN), then the

peripheral clock can be switched off.

So, how can the PERCLK, which derives from the IPG clock (which is called "peripheral clock") stay on in low power, when the clock it derives from turns off in low power?

There seems to be a lot of name confusion going on in the RM:

IPG_CLK is called "peripheral clock"

PERCLK_CLK is called "high frequency clock"

CKIH is called "external high frequency clock"

In any case, the PERCLK derives from the IPG_CLK. The IPG_CLK turns off in low power modes, so how is it possible that the PERCLK stays on? Is the Clock Tree diagram wrong? Is the description wrong? Or am I just missing some vital piece of information?

PS I verified that option 2 (high frequency clock) is indeed the PERCLK (at 66 MHz out of reset) and not the 24 MHz CKIH.

[igorpadykov]

Hi Michel

RM describes this conditionally:

"In low-power modes, if the EPIT is programmed to be disabled

(via STOPEN or WAITEN), then the peripheral clock can be switched off.

Best regards

chip

[MichaelV]

Hi Chip,

Yes, I know that. The question remains; if the peripheral clock (IPG_CLK) is programmed to be disabled (via STOPEN or WAITEN) so the IPG_CLK turns off, how can the "high frequency clock" (PERCLK_CLK) stay enabled when the PERCLK derives from the IPG_CLK?

[igorpadykov]

Hi Michel

(PERCLK_CLK) may be enabled only when IPG_CLK is enabled

(PERCLK derives from the IPG_CLK).

One needs to uderstand RM in that context (bearing in mind that there

may be inaccurate wording).

Best regards

chip

[MichaelV]

Hi Chip,

You are now contradicting the RM.

You say: PERCLK may only be enabled when IPG_CLK is enabled.

The RM says: This clock (PERCLK) remains on during low-power mode when the peripheral clock (IPG_CLK) is turned off.

So, we're at a point where we apparently both don't understand how this is supposed to work... :smileysad:

[igorpadykov]

Hi Michel

unfortunately this is inaccuracy in RM and I think probably you can find many similar

contradictions. Usually RM of previous processor is used for

writing new document as "template", using "copy&paste" method.

In Figure 18-2. CCM Clock Tree i.MX53 Reference Manual (rev.2.1  6/2012) one can see

that IPG_CLK_ROOT and PERCLK_ROOT are working

independently from each other, as RM states:

"This clock (PERCLK) remains on during low-power mode when the peripheral clock (IPG_CLK) is turned off."

<http://www.freescale.com/files/32bit/doc/ref_manual/iMX53RM.pdf>

Best regards

chip

[MichaelV]

I hope it is understood by Freescale that releasing Reference Manuals containing incorrect information is worse than not releasing any documentation at all!

[igorpadykov]

Hi Michel

soon new rev.2 of Reference Manual will be released.

Best regards

chip

[MichaelV]

If the iMX6SDL rev 2 is going to be anything like the iMX6DQ rev 2 then it won't be much better unfortunately...

For instance, in the iMX6DQ Rev 2 RM, the Clock Tree diagram now shows the location of the gates. This is great, but it is unclear which gates they are...

Look at the AHB_CLK_ROOT signal in the Clock Tree. You can see a gate (cg) on the left side of the divider (CBCDR[AHB_PODF]), but the clock root generator diagram on pdf page 822 doesn't show this gate. How can I find out which gate this is?

[igorpadykov]

this ahb_clk_root gate is described in

Table 18-3. System Clocks, Gating, and Override as

CCGR0[CG0] (aips_tz1_clk_enable)

CCGR0[CG1] (aips_tz2_clk_enable)

Best regards

chip

[MichaelV]

Chip,

I don't think those are the correct gates. I would expect the gates you mention to be on the right side of the divider. If the gates you mention are indeed at the location depicted in the Clock Tree, it would mean that closing either gate would also affect USDHC, and this we know is not true.

Please let me know if I am mistaken.