Hi,
I am trying to run DDR3 calibration for imx6 quad processor (MCIMX6Q5EYM10AC) with 4 memory chips (MT41K256M16TW-107) in flyby topology using only CS0. I am running V3.0 of the test script (aid document attached). Please see log below
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DDR Stress Test (3.0.0)
Build: Dec 14 2018, 14:12:06
NXP Semiconductors.
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Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.2
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Boot Configuration
SRC_SBMR1(0x020d8004) = 0x00000000
SRC_SBMR2(0x020d801c) = 0x30000001
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ARM Clock set to 1GHz
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DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 64, bank num: 8
Row size: 15, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
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Current Temperature: 43
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DDR Freq: 396 MHz
ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
MPWLHWERR register read out for factory diagnostics:
MPWLHWERR PHY0 = 0x00003878
HW WL cal status: no suitable delay value found for byte 2
HW WL cal status: no suitable delay value found for byte 3
MPWLHWERR PHY1 = 0x1e1e1e3c
Write leveling calibration completed but failed, the following results were found:
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x0043004E
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x001F001F
MMDC_MPWLDECTRL0 ch1 (0x021b480c) = 0x001D0030
MMDC_MPWLDECTRL1 ch1 (0x021b4810) = 0x00110015
Write DQS delay result:
Write DQS0 delay: 78/256 CK
Write DQS1 delay: 67/256 CK
Write DQS2 delay: 31/256 CK
Write DQS3 delay: 31/256 CK
Write DQS4 delay: 48/256 CK
Write DQS5 delay: 29/256 CK
Write DQS6 delay: 21/256 CK
Write DQS7 delay: 17/256 CK
WARNING: write-leveling calibration value is greater than 1/8 CK.
Per the reference manual, WALAT must be set to 1 in the register MDMISC(0x021B0018).
This has been performed automatically.
However, in addition to updating the calibration values in your DDR initialization,
it is also REQUIRED change the value of MDMISC in their DDR initialization as follows:
MMDC_MDMISC (0x021b0018) = 0x00011740
Error: failed during write leveling calibration
Please help.
Regards,
Sreedhar
