iMX6 DDR calibration in U-Boot

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iMX6 DDR calibration in U-Boot

Contributor I


I am dealing with DDR calibration on iMX6UL EVK.

I have modified defconfig file to use SPL and perform DDR calibration during SPL.  Source code for such calibration is found at 'arch/arm/mach-imx/mx6/ddr.c'.

Also, I have performed DDR calibration with 'DDR Stress Test Tool V3.00' (i.MX6/7 DDR Stress Test Tool V3.00 )

Regarding Read DQS Gating Calibration, I am getting different results with these two methods: with 'DDR Stress Test Tool V3.00', the calibration delay is about 1/4 cycle higher.

Looking at the source code at  'arch/arm/mach-imx/mx6/ddr.c', I see that in function 'modify_dg_result' a value of 0xc0 is substracted from upper boundary of automatic hw read calibration result.  Such value is equivalent to (1/2 + 1/4) cycle, when the reference manual states to substract 1/2 cycle.

I think there is a bug in 'modify_dg_result', and this explains the difference between u-boot ddr calibration and calibration with ddr stress tool.

Is this right or am I missing somethin?

Best Regards,


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Senior Contributor I


Please find below response:

1) I have done the DDR calibration with both the methods
    Method-i) 'DDR Stress Test Tool V3.00'
    Below is the screenshot for the parameters that I have used for calibrating DDR, please let me know if you have used different configurations.

    Note: Please see the DDR Freq, ARM Speed, DDR Density, MR1, and all the parameters and let me know if you configured any other values


 Read DQS Gating calibration register - MPDGCTRL0 PHY0 (0x021b083c) = 0x41500150 [ 1/2 + 0.3125 ]
    Attached Log File: "ddr_calibration_20190410-17'22'54.log"

    Method-i) u-boot ddr calibration (with SPL)
    Read DQS Gating calibration register - MPDGCTRL0 PHY0 (0x021b083c) = 0x41380138 [ 1/2 + 0.21875 ]
    Attached Log File: "uboot-ddr-calibration.txt"

In both the method, I saw the calibration delay to be approximately same, i.e DDR stress Tool and u-boot DDR calibration show the same calibration delay.


2) NXP does not support i.MX6UL SPL. Please find the reference of the same here - "". I would suggest to test the DDR calibration using only u-boot and not use SPL.




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