I am dealing with DDR calibration on iMX6UL EVK.
I have modified defconfig file to use SPL and perform DDR calibration during SPL. Source code for such calibration is found at 'arch/arm/mach-imx/mx6/ddr.c'.
Also, I have performed DDR calibration with 'DDR Stress Test Tool V3.00' (i.MX6/7 DDR Stress Test Tool V3.00 )
Regarding Read DQS Gating Calibration, I am getting different results with these two methods: with 'DDR Stress Test Tool V3.00', the calibration delay is about 1/4 cycle higher.
Looking at the source code at 'arch/arm/mach-imx/mx6/ddr.c', I see that in function 'modify_dg_result' a value of 0xc0 is substracted from upper boundary of automatic hw read calibration result. Such value is equivalent to (1/2 + 1/4) cycle, when the reference manual states to substract 1/2 cycle.
I think there is a bug in 'modify_dg_result', and this explains the difference between u-boot ddr calibration and calibration with ddr stress tool.
Is this right or am I missing somethin?