iMX53 NAND Connections

Showing results for 
Search instead for 
Did you mean: 

iMX53 NAND Connections

Contributor I

I am in the middle of developing a board similar to the iMX53 QSB and am trying to hookup 4 NAND chips to the iMX53 to hopefully boot off of.

My first issue is connecting the Ready/Busy lines.  I have not been able to find an example schematic showing two or more NAND chips sharing a bus.  My NAND datasheet explains that the R/B line is designed to be shared between chips since it is open drain.  However this seems like it would slow down the bus.  The iMX would have to wait until all chips were not busy since it does not know which chips are busy, only that one or more are busy.  This makes me think that each chip would get its own Chip Enable and Ready/Busy line and share everything else.

The iMX reference manual shows 4 separate Ready/Busy inputs internal to the iMX.  But I can only find one R/B line in the IO Mux planner and only one line in the datasheet for the iMX.  Does anyone have experience connecting multiple NAND chips to the iMX.  Does anyone have an example schematic?  Are the data lines, ALE, CLE, RE, and WE all shared?  Is Ready/Busy shared between NAND Chips or does each chip get its own line?

My second issue is I noticed in the datasheet that the iMX53 can boot off of NAND flash but that it is limited to CS0.  I am planning on using Ubuntu which would not entirely fit in one NAND flash chip.  However u-boot and the boot image would fit into the first chip.  Does that allow me to get around the CS0 limitation?  Once the iMX is running u-boot can it access the remaining 3 flash chips?

Also I cannot find a definite recommendation for decoupling caps on NAND chips.  Does anyone have value for caps they have used in a working application?

Thank you for any help you can offer,


Labels (2)
0 Kudos
2 Replies

NXP Employee
NXP Employee

Hi Corey,

I think I know where the confusion is. The i.MX53 has four internal r/b signals, one for each chip select. These four signals are OR'ed and output on a single pin, so externally, you have to control all your NANDs with a single r/b signal. So yes, all the chips will be ready or busy at the same time. I haven't seen reference design with this configuration, but the connection is very simple, just connect the RB signal of the i.MX to all NANDs with a single pull-up.

ALE, CLE, RE, WE and data signals are shared by all NANDs too. The only signal that's unique for each NAND is the chip select, that's how they know which one is the i.MX talking to.

About the second issue, I'll have to let someone in the software team to answer it. Deactivated user : Could you please help us find someone?

Best regards.


Contributor IV

So far as I understand, you could have four chips connected in parallel. In that case they would share every line except for an individual chip select. This connection is similar to a multichip module. This organization would be allowed for either 8b or 16b memories and it is certainly bootable on the lowest chip select, and the upper memories can be accessed once the bootloader gets control.

If you are using 8b memories, then it would also be possible to connect them into two banks of 16b each. This would only use two chip selects, since the upper/lower chips of one bank would share one chip select. I don't know if this configuration has any boot issues on the MX53; but I think that it is not supported with the MX6.


0 Kudos